T536
Industrial quad Cortex-A55 SoC with a RISC-V real-time core, inline DRAM ECC, 4x CAN-FD, 2x GbE MAC and a parallel Local Bus for FPGA links; no 3D GPU and no H.264/H.265 decode, so it is a controller, not a media chip.
- CPU
- 4x A55 up to 1.6 GHz + E907 RISC-V
- GPU
- None (2D G2D only)
- NPU
- Up to 3 TOPS (CEN3), 2 TOPS (CEN2), none (CEX, CXX)
- Video
- 4K25 H.264 enc, 4K15 MJPEG dec, no H.264/H.265 dec
- PCIe
- PCIe 2.1 x1 (shared with USB 3.1)
What the T536 is for
Right for
- Power-grid terminals (DTU, FTU, concentrators) and EV chargers that need 4x CAN-FD, up to 17 UARTs and two GbE MACs on one chip, rated -40 to 85 C ambient
- Controllers that pair Linux with a real-time side: a separate XuanTie E907 RISC-V core runs an RTOS or bare-metal code (Forlinx publishes an RT-Thread 5.0 port for it)
- FPGA or ASIC companions over a parallel bus: the Local Bus controller is 8, 16 or 32 bits wide at up to 100 MHz bus clock
- Designs that must protect DRAM from bit errors: three of the four SKUs support inline ECC on 32-bit DDR3/DDR4/LPDDR3/LPDDR4/4X, with ECC on the CPU caches too
- Multi-camera capture and encode: four MIPI CSI ports (4+4, 4+2+2 or 2+2+2+2 lanes), an 8 MP ISP and a 4K25 H.264 encoder
Wrong for
- Anything that plays H.264 or H.265 video: the hardware decoder handles MJPEG and JPEG only
- GPU-rendered UIs: there is no 3D GPU, only the G2D 2D engine (rotate, mix, scale)
- HDMI or eDP output: displays are MIPI DSI, dual-link LVDS or parallel RGB up to 1920x1200 at 60 Hz, and the three share pins
- Designs needing PCIe and USB 3 at once, or more than one PCIe lane: one combo PHY carries either USB 3.1 Gen1 or PCIe 2.1 x1
- Products that must run on mainline Linux today: as of 7.3-rc7 there is no T536 support upstream, only an RFC posted in April 2026
Cost and constraints
- BOM is the SoC plus Allwinner companion PMICs: AXP717D (QFN-52, 6 x 6 mm, 4 bucks, 14 LDOs) and AXP323 (QFN-20, 3 x 3 mm, 3 bucks) on the Boardcon PICOT536, the pairing MT-System also names
- ED-FCCSP 533 balls, 15 x 15 mm, 0.5 mm pitch, 0.3 mm balls: public modules use 8-layer (Boardcon), 10-layer (Forlinx) and 12-layer (MYIR) boards
- SKU choice is fixed at order time: the NPU exists only on CEN3 (3 TOPS) and CEN2 (2 TOPS); the CXX has neither NPU nor ECC
- No bare-chip price or stock at LCSC; distributor access is by inquiry (MT-System in Russia publicly), so most products start from a SoM
- Vendor SDKs (Linux 5.10.198 on Forlinx, 5.10 on MYIR, 5.15.147 on Boardcon) come from the module vendor after purchase; no public Allwinner SDK repository was found
Inside the T536
Drawn by Groundplane from the product brief v0.90. Not Allwinner artwork.
- 32-bit DDR3/DDR4/LPDDR4/4X
- eMMC 5.1, SD 3.0
- Octal SPI NOR/NAND
- 8-bit raw NAND
- 4x Cortex-A55 up to 1.6 GHz
- 64 KB L2 per core, 512 KB L3
- ECC on L1, L2 and L3
- XuanTie E907 RISC-V, 600 MHz
- E902 RISC-V power manager
- Up to 3 TOPS (CEN3 only)
- 4K25 H.264 encoder
- MJPEG/JPEG decoder
- Distortion-correcting ENCPP
- G2D 2D engine
- 32-bit DDR controller
- Inline ECC
- Up to 8 GB
- Display engine
- MIPI DSI, LVDS, RGB
- ISP 8 MP at 30 fps
- MIPI CSI up to 4 ports
- Parallel CSI
- Crypto engine, SM2/3/4
- TRNG, 2 Kbit eFuse
- TrustZone, secure boot
- CCU, PRCM, message box
- Thermal sensor, timers, WDT
- USB 3.1 Gen1 or PCIe 2.1 x1
- USB 2.0 DRD, USB 2.0 host
- 2x GbE MAC (RGMII/RMII)
- Local Bus 8/16/32-bit
- SDIO 3.0
- MIPI DSI x4, dual LVDS, RGB
- MIPI CSI 4+4 lanes, parallel CSI
- 4x CAN-FD, 17x UART
- 9x TWI, 6x SPI, 34x PWM
- I2S x4, DMIC, LINEOUT
Read from the documents
Each value names the document it was read from.
| CPU | 4x Cortex-A55, 32 KB L1 I/D, 64 KB L2 per core, 512 KB L3, ECC on L1, L2 and L3; XuanTie E907 RISC-V MCU (16 KB I/D cache with ECC); E902 RISC-V for low-power management | Product brief V0.90, Processors |
|---|---|---|
| CPU clock | Cortex-A55 up to 1.6 GHz; E907 up to 600 MHz | Other, Specifications table |
| GPU | No 3D GPU. G2D 2D accelerator (rotate, mixer, scaler) and SmartColor 2.0 display post-processing | Product brief V0.90, Display Engine |
| NPU | Up to 3 TOPS (T536MX-CEN3) or up to 2 TOPS (T536MX-CEN2); none on CEX and CXX. INT8, UINT8 and INT16; 512 KB built-in SRAM shareable with the system | Datasheet V0.90, Table 2-1, 3.1 |
| Video decode | MJPEG up to 4K at 15 fps; JPEG baseline up to 1080p60. No H.264 or H.265 decode. Decoder and encoder are time-multiplexed | Product brief V0.90, Video Engine |
| Video encode | H.264 up to 4K at 25 fps; MJPEG up to 4K at 15 fps; JPEG up to 8K x 8K; encoder pre-processing with geometric, lens and fisheye distortion correction | Product brief V0.90, Video Engine |
| ISP | 8 MP at 30 fps offline (up to 4800 x 4224), 5 MP at 30 fps online (up to 2688 x 4224); time-division multiplexing across sensors | Product brief V0.90, ISP |
| Memory | 32-bit DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, LPDDR4X, 2 ranks, up to 8 GB, with inline ECC on CEN3, CEN2 and CEX; clock up to 1066 MHz (DDR3, DDR3L, LPDDR3) and 1400 MHz (DDR4, LPDDR4, LPDDR4X). No inline ECC with a 16-bit BL8 DRAM, and no 6 GB (4 + 2 GB) LPDDR3 map with ECC enabled | Datasheet V0.90, 3.2.3 |
| Storage | Boot from SD 3.0, eMMC 5.1 (both with ECC protection), SPI NOR/NAND or raw NAND; 8-bit parallel NAND with 80-bit/1 KB BCH; one octal SPI flash interface | Product brief V0.90, Memory |
| Display | 4-lane MIPI DSI up to 1920 x 1200 at 60 Hz (reduced blanking); dual-link LVDS up to 1920 x 1080 at 60 Hz; one parallel RGB (DE/SYNC) up to 1920 x 1200 at 60 Hz | Product brief V0.90, Video Output |
| Camera | MIPI CSI-2 as 4+4, 4+2+2 or 2+2+2+2 lanes at up to 2.0 Gbps per lane, 8 MP at 30 fps on 4 lanes; parallel CSI 8/10/12/16-bit, BT.656 up to 4x 720p30, BT.1120 up to 4x 1080p30 | Product brief V0.90, Video Input |
| PCIe | 1x PCIe 2.1 x1 on a combo PHY shared with USB 3.1; RAS data protection with ECC on PCIe RAMs | Product brief V0.90, Connectivity |
| USB | 1x USB 3.1 Gen1 DRD (shares its PHY with PCIe), 1x USB 2.0 DRD, 1x USB 2.0 host | Product brief V0.90, Connectivity |
| Ethernet | 2x GMAC, 10/100/1000 Mbps, RGMII or RMII | Product brief V0.90, Connectivity |
| Audio | One DAC with differential LINEOUT; 4x I2S/PCM (up to 16 channels, 8 to 384 kHz); up to 8 PDM microphones; OWA (S/PDIF) in and out | Product brief V0.90, Audio |
| Security | AES, DES, 3DES, SM4; MD5, SHA, SM3; RSA, ECC, SM2; 256-bit TRNG; 2048-bit eFuse; TrustZone, secure boot | Product brief V0.90, Security Engine |
| Other I/O | 4x CAN-FD, 1x Local Bus, 17x UART, 9x TWI, 6x SPI, 34-ch PWM, 21-ch GPADC, 4-ch TPADC, 1-ch LRADC, 5x IR RX, 1x IR TX, SDIO 3.0, LEDC | Product brief V0.90, Industrial and general connectivity |
| Process | 22 nm ULP | Product brief V0.90, Process |
| Package | ED-FCCSP, 533 balls, 15 x 15 mm, 1.056 mm max height, 0.5 mm ball pitch, 0.3 mm ball size | Datasheet V0.90, Device Summary, 3.12 |
| Temperature | Industrial, -40 to 85 C ambient; recommended Tj -40 to 110 C, absolute max Tj 125 C | Datasheet V0.90, Table 6-1, Table 6-2 |
| Thermal | theta-JA 23.04 C/W and theta-JB 8.64 C/W (JEDEC still air, 4-layer 114.5 x 76.2 mm board); theta-JC not given; three on-chip thermal sensors | Datasheet V0.90, Table 6-3, 3.8.6 |
Variants
| T536MX-CEN3 | NPU up to 3 TOPS; DRAM ECC supported. Industrial grade, ED-FCCSP 533. | Product brief V0.90 |
|---|---|---|
| T536MX-CEN2 | NPU up to 2 TOPS; DRAM ECC supported. This is the part Allwinner describes on its product page and the one Forlinx, MYIR (NPU SKUs) and Boardcon fit. | Product brief V0.90 |
| T536MX-CEX | No NPU; DRAM ECC supported. MYIR uses it on its non-NPU MYC-LT536 SKUs. | Product brief V0.90 |
| T536MX-CXX | No NPU and no ECC protection. | Product brief V0.90 |
What to watch when you design with it
Power and PMIC
MT-System, Allwinner's Russian distributor, names AXP717D and AXP323 as the companion PMICs for the T536, and the Boardcon PICOT536 manual lists both on that module. AXP717D takes 3.9 to 5.5 V and provides four bucks (DCDC1 0.5 to 1.54 V at 4 A, DCDC2 0.5 to 3.4 V at 3 A, DCDC3 0.5 to 1.84 V at 1.5 A, DCDC4 1.0 to 3.4 V at 3 A) plus 14 LDOs, in QFN-52 6 x 6 mm. AXP323 adds three 3 A COT bucks, with DCDC1 and DCDC2 able to run dual-phase for 5 A, in QFN-20 3 x 3 mm. Forlinx feeds its SoM 5 V and asks the carrier for at least 2 A continuous; Boardcon accepts 3.4 to 5.5 V. Forlinx gates every carrier-board DC-DC from the SoM 3.3 V rail so the SoC powers first, to avoid latch-up, and tells custom carriers to keep that sequence.
Sources: Other, Other V1.202603, PMIC V1.1, PMIC V1.1, Other V1.2
DDR
One 32-bit channel, up to 8 GB, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4 or LPDDR4X. Inline ECC (CEN3, CEN2, CEX) has two limits in the brief: no ECC when a BL8 DRAM (DDR3, DDR4, LPDDR3, BL8 LPDDR4) is only 16 bits wide, and no 6 GB (4 + 2 GB) LPDDR3 map with ECC on. Every public module uses LPDDR4 (Forlinx, MYIR) or LPDDR4/4X (Boardcon, up to 8 GB). No public Allwinner DDR layout guide or routing rules were found; copy a module vendor layout or ask Allwinner for the design kit.
Sources: Product brief V0.90, Other, Other, Other V1.202603
High-speed interfaces
The USB 3.1 Gen1 port and PCIe 2.1 share one combo PHY, so the board picks one; Forlinx and Boardcon add an analog switch or share the lane with an M.2 or mPCIe slot. The USB 2.0 half of the USB 3.1 port also shares a PHY with USB1, so at most two native USB 2.0 ports run at once. PCIe can be root complex or endpoint. Forlinx impedance targets: USB 2.0 and USB 3.0 90 ohm differential, PCIe, MIPI CSI, MIPI DSI and LVDS 100 ohm, SDIO 50 ohm. Its length rules: USB 3.0 and PCIe intra-pair 5 mil or less, total under 5000 mil, at most two vias; MIPI CSI inter-pair within 300 mil; Local Bus data, address and command matched to the clock within 300 mil (500 mil maximum) at 150 MHz. For 4-lane CSI only MCSIA with MCSIB, or MCSIC with MCSID, can pair, and the clock of the first port is used.
Sources: Product brief V0.90, Other V1.2, Other V1.202603
Boot and FEL
The boot ROM can boot from SD 3.0, eMMC 5.1, SPI NOR/NAND or raw NAND. A FEL pin, active low, forces USB download mode over the USB0 OTG port; Forlinx and Boardcon both bring it out as a FEL button. Boot order is set by a resistor divider on an ADC boot-select pin: Forlinx puts a 10 k pull-up to 1.8 V on the SoM and a 3.9 k 1% pull-down on the carrier for the order SD (SMHC0), eMMC boot partition, eMMC user area, then others except SPI2. Because SD is tried first, a card with a boot partition in the slot will boot instead of eMMC. Forlinx says not to put any resistor or capacitor on AP-RESET.
Sources: Product brief V0.90, Other V1.2, Other V1.202603
Thermal
Forlinx measured its FET536-C (CEN2, 2 GB, 16 GB eMMC) at 2.92 W under a CPU, memory and eMMC stress test, 1.44 W running the NPU demo and 0.61 W in sleep, from 5 V. It runs the SoM bare and offers an optional 39 x 39 x 23 mm heatsink with a thermal pad. The datasheet gives theta-JA 23.04 C/W and theta-JB 8.64 C/W on a JEDEC 4-layer board, with a recommended junction ceiling of 110 C and three on-chip sensors for throttling.
Sources: Other V1.2, Datasheet V0.90
Gotchas
Three debug UARTs: Forlinx brings out UART0 for the A55 cluster, a CPUS UART for the E902 and S-UART1 for the E907, and recommends keeping all of them on custom carriers. S-TWI0 is used by the PMIC on the module. SMHC1 (SDIO) runs in 1.8 V mode only on the Forlinx module. The 32.768 kHz clock output for Wi-Fi modules is open drain and needs an external pull-up to the module's I/O voltage. RGB, LVDS and MIPI DSI share pins, so plan one display path. Vendor numbers disagree: Allwinner's product page lists 31 GPADC channels and 16384 x 16384 JPEG decode where the brief lists 21 channels and 1080p60 JPEG decode.
Sources: Other V1.2, Other, Other, Product brief V0.90
Layout guides for the T536's interfaces
Public layout guidance for each interface this chip has, from vendors who publish it, plus our calculators.
LPDDR4
Point-to-point routing; TI notes that on-die termination on both ends means no board termination is needed. Byte lanes length-matched to their strobe and command/address matched to the clock, all over a solid reference plane. Impedance targets differ by vendor: TI AM62x and ADI EE-480 use 40 ohm single-ended and 80 ohm differential, Synaptics SL1680 uses 50 and 85 ohm, AMD Versal 45 and 82 ohm. Use the SoC vendor's own target and simulate.
- AM62x, AM62Lx DDR Board Design and Layout GuidelinesTexas Instruments, SPRAD06, C, 2025
- AM62Ax, AM62Px, AM62Dx LPDDR4 Board Design and Layout GuidelinesTexas Instruments, SPRAD66, B, 2024
- ADSP-2184x/ADSP-SC84x LPDDR4 Board Design GuidelinesAnalog Devices, EE-480, 1, 2026
- SL1680 General PCB Design and LPDDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001390-01, E
- DDR length matching calculatorGroundplane calculator
LPDDR4X
Same topology and matching discipline as LPDDR4, with a lower I/O voltage, so routing rules are usually published for both together. Synaptics SL1680 gives 50 ohm single-ended and 85 ohm differential for LPDDR4 and LPDDR4X; AMD Versal gives 45 and 82 ohm. Check the SoC vendor target before fixing the stackup.
- SL1680 General PCB Design and LPDDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001390-01, E
- SL1640 General PCB Design and DDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001529-01, D
- Versal Adaptive SoC PCB Design User Guide: PCB Routing Guidelines for LPDDR4/4x InterfacesAMD, UG863, 1.12, 2026
- DDR length matching calculatorGroundplane calculator
DDR4
DDR4 uses pseudo open-drain data signaling and needs a VPP supply, with command/address routed fly-by or as a balanced tree depending on device count. TI AM62x uses 40 ohm single-ended and 80 ohm differential; AMD Versal uses 50 and 90 ohm, relaxed under the BGA. Match data to strobe per byte and command/address to clock.
- AM62x, AM62Lx DDR Board Design and Layout GuidelinesTexas Instruments, SPRAD06, C, 2025
- Versal Adaptive SoC PCB Design User Guide: PCB Routing Guidelines for DDR4 InterfacesAMD, UG863, 1.12, 2026
- SL1640 General PCB Design and DDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001529-01, D
- PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex 5 FPGAs and SoCsAltera, 821801, 2026
- DDR length matching calculatorGroundplane calculator
- Via current calculatorGroundplane calculator
DDR3 / DDR3L
Fly-by command/address with termination at the end of the chain, point-to-point data lanes matched to their strobe, and a clean VREF. ST recommends 55 ohm single-ended and 100 ohm differential for DDR3 and DDR3L on STM32MP1 boards, and shows that a 4-layer board is possible with strict layer allocation.
- STM32MP1 Series DDR memory routing guidelinesSTMicroelectronics, AN5122, 3, 2019
- DDR3 Design Requirements for KeyStone DevicesTexas Instruments, SPRABI1, D, 2022
- SL2610 General PCB Design and DDR3L/DDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001629-01, A, 2025
- DDR length matching calculatorGroundplane calculator
LPDDR3
Point-to-point and normally unterminated, with command/address matched to the clock and each byte matched to its strobe. ST gives the same targets for LPDDR3 as for DDR3: 55 ohm single-ended and 100 ohm differential. Few current public guides cover LPDDR3, so treat the SoC vendor's reference layout as the stronger source.
- STM32MP1 Series DDR memory routing guidelinesSTMicroelectronics, AN5122, 3, 2019
- DDR length matching calculatorGroundplane calculator
eMMC
A single-ended bus: CLK, CMD, DAT0 to DAT7 and, for HS400, the data strobe. TI and Synaptics both route it at 50 ohm single-ended, match the group, and keep stubs short; Synaptics places a 22 or 33 ohm series resistor on CLK and STRB. At HS400 TI also checks the eMMC I/O supply impedance, not just the traces.
- AM62Px eMMC HS400 Board Design and Simulation GuidelinesTexas Instruments, SPRADP5, A, 2026
- Astra Machina Foundation Series eMMC ConfigurationSynaptics, PN 506-001594-01, D
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
SD card / SDIO
Single-ended CLK, CMD and four data lines over a solid ground plane, at constant trace width and matched length. NXP asks for clock-to-neighbor spacing greater than twice the trace height above the plane and 1.5 times for data and CMD, with 45 degree bends. UHS modes switch the I/O to 1.8 V, so a level translator often sits next to the socket.
- NVT4557/NVT4558/NVT4858 voltage-level translator layout guidelineNXP, AN13158, 1.1, 2022
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
- SD Physical Layer Simplified SpecificationSD Association, 9.10, 2023
PCIe
AC-coupled differential lanes routed with no stubs, minimal vias and back-drilled or blind vias where speed demands, with lane-to-lane skew handled by the receiver. Targets differ by guide: TI Jacinto 7 uses 85 ohm differential for lanes and 100 ohm for the reference clock, while TI's earlier SoC guide tabulates 100 ohm and, for some devices, 95 ohm. Match the target to your connector and stackup.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
USB 3.x
SuperSpeed TX and RX pairs are routed at 90 ohm differential in all three TI guides (SPRAAR7 lists 95 ohm for some devices), with AC coupling capacitors on TX, symmetric pad and via placement, and matched via counts within each pair. Keep the pairs away from the USB 2.0 pair and other aggressors, and place ESD at the connector.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
USB 2.0
One D+/D- pair at 90 ohm differential, routed in parallel for its whole length with minimal deviations at the connector and package. NXP keeps clocks and periodic signals at least 50 mils away and other signals at least 20 mils away from the pair.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
MIPI DSI
MIPI D-PHY clock and data lanes are routed as 100 ohm differential pairs over a solid reference; TI Jacinto 7 allows no stubs, 2 vias per trace and 40 ps lane-to-lane skew. Connectors and flex cables to the panel are usually the largest discontinuity, so keep the board segment short and clean.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex 5 FPGAs and SoCsAltera, 821801, 2026
MIPI CSI-2
Same D-PHY rules as DSI: 100 ohm differential lanes in both TI guides, with lane-to-lane skew bounded (40 ps in TI Jacinto 7). Size the lane count and lane rate from the sensor's output format before routing.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex 5 FPGAs and SoCsAltera, 821801, 2026
- MIPI CSI-2 bandwidth calculatorGroundplane calculator
LVDS
Tightly coupled differential pairs terminated at the receiver in 100 ohm, with TI's EMI guide asking for 100 ohm differential traces within 5 percent. Keep pairs matched and away from other aggressors, and avoid stubs and reference plane gaps along the route to the panel connector.
- LVDS Owner's Manual: Including High-Speed CML and Signal ConditioningTexas Instruments, SNLA187, 4th edition, 2008
- High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes DesignsTexas Instruments, SNLA302, 2018
- LVDS SerDes Gen I PCB and Interconnect Design-In GuidelinesTexas Instruments, SNLA008, A, 2018
Ethernet (RGMII / RMII)
TI routes MAC-to-PHY (MII family) traces at 50 ohm single-ended, under 6 inches, matched within 20 mils for gigabit, and the PHY-side MDI pairs at 100 ohm differential. RGMII also needs a 1.5 to 2.0 ns clock-to-data delay, added on the board or inside the MAC or PHY (RGMII-ID); decide which before layout so it is not applied twice.
- Ethernet PHY PCB Design Layout ChecklistTexas Instruments, SNLA387, 2021
- PCB Design Guideline for RGMII InterfaceRenesas, R01AN6272EJ0141, 1.41, 2026
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
Board-level design guides
Impedance and timing, power, thermal and ESD guidance that applies to any board around this chip.
Impedance and timing
Every high-speed interface on the board comes down to the same two numbers: the trace impedance your stackup actually gives, and the delay each trace adds. Set the stackup with your fab first, then route to its impedance table and match lengths in time, not millimeters, where the layers differ.
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- PCB impedance calculatorGroundplane calculator
- PCB propagation delay calculatorGroundplane calculator
Power delivery
For each switching regulator, place and route the input capacitor first, keep the switching current loop small, and keep the switch node short. Give the SoC rails solid planes and decoupling at the balls, and size current-carrying copper and vias for the real load.
- Five steps to a great PCB layout for a step-down converterTexas Instruments, SLYT614, 2015
- AN-1149 Layout Guidelines for Switching Power SuppliesTexas Instruments, SNVA021, C, 2013
- AN-1229 SIMPLE SWITCHER PCB Layout GuidelinesTexas Instruments, SNVA054, C, 2013
- Buck converter calculatorGroundplane calculator
- LDO power dissipation calculatorGroundplane calculator
- PCB trace width calculatorGroundplane calculator
- Via current calculatorGroundplane calculator
Thermal
Theta-JA is measured on a JEDEC test board that carries most of the heat, so it does not transfer directly to a product board; use it to compare packages and use the psi metrics for estimates. Thermal vias under the package, copper area and copper thickness move the most heat into the board.
- Semiconductor and IC Package Thermal MetricsTexas Instruments, SPRA953, D, 2024
- AN-2020 Thermal Design By Insight, Not HindsightTexas Instruments, SNVA419, C, 2013
- Heatsink thermal resistance calculatorGroundplane calculator
- LDO power dissipation calculatorGroundplane calculator
ESD protection
Place the TVS as close to the connector as design rules allow, route from the connector to the TVS with no stub, and keep the protected IC further from the TVS than the TVS is from the connector. Choose parts by clamping performance and by capacitance low enough for the interface speed.
- ESD Protection Layout GuideTexas Instruments, SLVA680, A, 2022
- Reading and Understanding an ESD Protection Data SheetTexas Instruments, SLLA305, A
- TPD12S016 PCB Layout Guidelines for HDMI ESDTexas Instruments, SLLA324, 2012
- PCB conductor spacing calculator (IPC-2221)Groundplane calculator
Allwinner's hardware design guide
Allwinner's hardware design guide, EVB reference schematics and DDR templates come from Allwinner or an authorized agent, usually under NDA, or through your SoM vendor. We do not link copies circulating elsewhere. The vendor schematics and open designs on the Boards tab are real, shipped layouts on the T536 and the best public reference.
BSP, mainline and toolkits
| Area | Status | Links |
|---|---|---|
| Vendor BSP kernel | Allwinner describes the platform as an AMP system running Tina Linux alongside an RTOS or bare-metal code on the RISC-V core. Module vendors ship their own SDKs after purchase: Forlinx Linux 5.10.198 with Buildroot and Qt 5.15.8, MYIR Linux 5.10 with U-Boot 2022.10 and TF-A, Boardcon Buildroot with Linux 5.15.147 and U-Boot 2023.04. No public Allwinner kernel repository for T536 was found.Checked 2026-10-13 | |
| Mainline Linux | Not supported as of 7.3-rc7: no T536 device tree, clock or pinctrl driver in torvalds/linux. An RFC on the linux-sunxi list (2026-04-16) reports clocks, pinctrl with GPIO interrupts, a UART console and an initramfs boot on a T536 EVB; Andre Przywara noted the GPIO block matches the new A733 layout and asked for full clock, PMIC and RTC series before the device tree. The work-in-progress branch was last updated 2026-04-16.Checked 2026-10-13 | |
| U-Boot | No T536 support in mainline U-Boot or TF-A on 2026-10-13. Vendor SDKs use Allwinner's U-Boot fork (2022.10 on MYIR, 2023.04 on Boardcon).Checked 2026-10-13 | |
| RISC-V core | Forlinx publishes an RT-Thread 5.0.0 port described as "rt-thread for T536" (last push 2024-12-16). Forlinx lists Linux RT, FreeRTOS and bare metal on the E907.Checked 2026-10-13 | |
| Distributions | Vendor images only: Forlinx Buildroot with Qt and Forlinx Desktop 20.04, MYIR Buildroot images, Boardcon Buildroot. No Armbian, Debian or OpenWrt support found.Checked 2026-10-13 | |
| Community | linux-sunxi has a T536 summary page; the linux-sunxi mailing list carries the upstreaming discussion.Checked 2026-10-13 |
T536 system on modules
Any of these can sit on a carrier board we design.
| Module | Vendor | Connector | RAM | Design files | Price |
|---|---|---|---|---|---|
| FET536-C | Forlinx | 4x 80-pin 0.5 mm board-to-board, 2.0 mm mating height | 1 or 2 GB LPDDR4 | Product brief and online hardware manual public; datasheet, carrier schematic and PCB, pinmux after purchase | |
| FET536-UP4 | Forlinx | 487-pin hybrid LCC (1.0 mm) and LGA (1.27 mm), UP4 pin-compatible family | 1, 2 or 4 GB LPDDR4 | ||
| MYC-LT536 | MYIR | 381-pin LGA | 1, 2 or 4 GB LPDDR4 | Datasheet and 3D STEP public; schematics and BSP on request | USD 74 (MYIR sample price, 1 GB, 8 GB eMMC, no NPU) |
| PICOT536 | Boardcon | MXM 3.0 314-pin card edge | 2, 4 or 8 GB LPDDR4/4X with inline ECC | Hardware manual PDF (V1.202603), 3D model, connector datasheet | |
| ECK33-B series (ECK33-BCE2E16-I, ECK33-B2N4E32-I) | Ebyte | LGA | 2 GB (16 GB storage) or 4 GB (32 GB storage) |
Every public T536 board
| Board | Vendor | Type | RAM | Notable I/O | Design files | Price |
|---|---|---|---|---|---|---|
| OK536-C | Forlinx | Dev kit, 130 x 190 mm, 4-layer, 12 V input | 1 or 2 GB LPDDR4 | 2x GbE, USB 3.0 or PCIe x1 slot (switched), 4x isolated CAN-FD, 2x RS-485, RGB, LVDS, DSI via adapter, 3x MIPI CSI via adapter (shared with Local Bus) | Carrier schematic and PCB after purchase | |
| OK536-UP4 | Forlinx | Dev kit | 1, 2 or 4 GB LPDDR4 | 2x GbE, USB 3.0, MIPI CSI 4+2+2 lanes, MIPI DSI, LVDS, 2x isolated CAN, 2x RS-485 | Carrier schematic and PCB listed as downloads (access not checked) | |
| MYD-LT536 (GK kit) | MYIR | Dev kit | 2 or 4 GB LPDDR4 | 2x GbE plus USB 10/100, NVMe M.2 2280, LVDS, Wi-Fi, BT, Local Bus, RPi and MiFAN headers | Overview PDF and quick start guide public; schematics on request | USD 149 (MYIR sample price, 2 GB, no NPU) |
| EMT536 | Boardcon | SBC, 180 x 120 mm | 2, 4 or 8 GB LPDDR4/4X | 2x GbE, M.2 M-key NVMe (shared with USB 3.0), MIPI DSI or dual LVDS, 2x CAN, 2x RS-485, 9x UART, mPCIe 4G | Buildroot user manual; no schematic listed | |
| ECB33-PGB2N4E32-I | Ebyte | SBC, 146 x 101 mm | 4 GB, 32 GB storage | MIPI DSI, MIPI CSI, Local Bus, Ethernet, CAN, RS-485, Mini PCIe |
Prices and links as checked on the dates in our data; the latest check on this page was 2026-10-13.
Buying the chip
No public bare-chip price or MOQ was found. In practice the part is bought on a module: MYIR publishes sample prices from USD 74 (MYC-LT536, 1 GB, no NPU); Forlinx, Boardcon and Ebyte quote on request.
- MT-System (Russia)
- States it signed a distribution contract with Allwinner on 2023-02-17; lists the four T536 SKUs and takes orders by inquiry (semi@mt-system.ru). No public price.
- Allwinner direct
- The product brief gives service@allwinnertech.com as the contact. No distributor list is published on the product page.
- LCSC
- No T536 SoC listing.
Datasheet, TRM and design documents
Linked where they are publicly hosted; we do not rehost Allwinner documents. These are third-party documents: we are not responsible for their accuracy, availability or confidentiality status. Disclosure.
- DatasheetAllwinner T536 Family DatasheetV0.90 · 2024-11-14 · hosted by MT-System (Allwinner distributor) · checked 2026-10-13
- Product briefAllwinner T536 Brief (Quad-core 64-bit Industrial Device Processor)V0.90 · 2024 · hosted by MT-System (Allwinner distributor) · checked 2026-10-13
- OtherT536 product page (describes T536MX-CEN2)hosted by Allwinner · checked 2026-10-13
- PMICX-Powers AXP717D DatasheetV1.1 · 2024-05-07 · hosted by MT-System (Allwinner distributor) · checked 2026-10-13
- PMICX-Powers AXP323 DatasheetV1.1 · 2023-05-04 · hosted by MT-System (Allwinner distributor) · checked 2026-10-13
- OtherForlinx OK536x-C User's Hardware Manual (SoM, carrier, design guide)V1.2 · 2025-12-11 · hosted by Forlinx · checked 2026-10-13
- OtherForlinx FET536-C SoM and OK536-C product brief2025 · hosted by Forlinx · checked 2026-10-13
- OtherMYIR MYC-LT536 SoM datasheethosted by MYIR · checked 2026-10-13
- OtherBoardcon PICOT536 Reference User Manual (AXP717D + AXP323)V1.202603 · 2026-03 · hosted by Boardcon · checked 2026-10-13
- OtherMT-System: T536 available to order (names AXP717D and AXP323, links the brief and PMIC datasheets)2025-01-21 · hosted by MT-System · checked 2026-10-13
Questions about the T536
Not the T536 itself. We have designed and brought up boards on the Allwinner T507 and A527/T527, and on the Rockchip RV1106, RV1126, RV1126B, RK3566, RK3568, RK3576 and RK3588. The work carries over: power tree, DDR and high-speed layout, bring-up and the BSP, read against this chip's own datasheet.
MT-System, an Allwinner distributor, hosts the T536 Family Datasheet V0.90 (2024-11-14) and the T536 Brief V0.90, together with the AXP717D and AXP323 PMIC datasheets. The datasheet is stamped Confidential on every page, as Allwinner datasheets are. Forlinx's online hardware manual is the most detailed public design reference.
CEN3 has an NPU of up to 3 TOPS, CEN2 up to 2 TOPS, CEX and CXX have no NPU. CEN3, CEN2 and CEX support DRAM ECC; CXX does not. All four are industrial grade in the same 533-ball 15 x 15 mm package. The public modules use CEN2 (Forlinx, Boardcon, MYIR NPU SKU) or CEX (MYIR non-NPU SKUs).
No. The decoder handles MJPEG up to 4K15 and JPEG only; the encoder does H.264 up to 4K25. Display outputs are MIPI DSI, dual-link LVDS and parallel RGB up to 1920 x 1200 at 60 Hz. Boardcon adds HDMI through a DSI-to-HDMI bridge on its module. For video playback, look at A527/T527 or a Rockchip part instead.
Not yet. As of 7.3-rc7 there is no T536 support in the kernel, U-Boot or TF-A. A community RFC in April 2026 boots an initramfs with clocks, pinctrl and UART, and maintainers asked for full clock, PMIC and RTC series first. Production work uses the vendor SDKs: Linux 5.10 (Forlinx, MYIR) or 5.15 (Boardcon).
AXP717D plus AXP323, both from Allwinner's X-Powers. MT-System names the pair for the T536 and the Boardcon PICOT536 manual lists both on board. AXP717D supplies four bucks and 14 LDOs from 3.9 to 5.5 V; AXP323 adds three 3 A bucks, two of which can be paralleled for 5 A.
Forlinx FET536-C (4x 80-pin board-to-board, 45 x 68 mm) and FET536-UP4 (487-pin LCC/LGA, 40 x 40 mm); MYIR MYC-LT536 (381-pin LGA, 43 x 45 mm, from USD 74); Boardcon PICOT536 (MXM 3.0 edge, up to 8 GB); Ebyte ECK33-B (LGA, 45 x 43 mm). Each has a matching dev kit.
Related chips and reading
- A527 / T527Industrial HMI, dual-display terminals, gateways, robots, tablets
- T113HMI panels, CAN gateways, car displays, small Linux controllers
- A733Tablets, interactive displays, compact edge AI SBCs
- RK3568Routers, NAS, gateways, NVR, industrial HMI
- RK3562Cost-down HMI, tablets, industrial gateways
- RK3576Edge AI boxes, HMI, NVR, Arm PC, tablets
- RV1126BAI IP cameras, multi-camera vision
We'll design your T536 board.
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Links and facts on this page checked 2026-10-13. Spotted something out of date? Tell us through the contact form.
Compiled from publicly available sources: datasheets, technical reference manuals, vendor product pages, schematics and source code published by their owners and third parties. We link to documents where others host them and do not host, endorse or vouch for them. Everything on these pages, including our own specs, summaries, block diagrams, comparisons, calculators and design notes, is for reference only and may contain errors or be out of date. It is provided as is, and Groundplane is not responsible for errors in it, for third-party documents, or for any design, board or decision based on it. Always check the manufacturer's current datasheet, reference manual and design guidance before you design a board. Rockchip, Allwinner, Raspberry Pi and other product names are trademarks of their owners; we are not affiliated with any of them. See our disclosure.