WarpKVM 01, our 4K KVM, runs on it. Case study: WarpKVM
RK3576
Mid-range Rockchip SoC with the same 6 TOPS NPU as RK3588 but 4x A72 + 4x A53, 8K30 decode and UFS 2.0, limited to two PCIe 2.1 x1 lanes, 32-bit LPDDR4/5 and a 16 GB address space; bare chips from about USD 21 to 23 at LCSC.
- CPU
- 4x A72 2.2 GHz + 4x A53 2.0 GHz
- GPU
- Mali-G52 MC3
- NPU
- 6 TOPS INT8 (INT4 to FP16, BF16, TF32)
- Video
- 8K30 H.265/VP9/AV1/AVS2 decode, 4K60 H.265/H.264 encode
- PCIe
- 2x PCIe 2.1 x1 (shared with SATA and USB3)
What the RK3576 is for
Right for
- Edge AI appliances that need the 6 TOPS NPU and RKNN toolchain at a lower BOM than RK3588
- Multi-display HMI and signage: three independent video ports (4K120 + 2560x1600 + 1080p) across HDMI 2.1, DP 1.4, eDP and DSI
- Camera products: 16 MP ISP, up to 5 CSI-2 groups through VICAP, D-PHY 2.0 / C-PHY 1.1 on one port
- UFS 2.0 boot and storage designs, which RK3588 does not offer
- Industrial controllers: two GMACs, two CAN ports, 12 UARTs with RS485 control, RK3576J at -40 to 85 C
Wrong for
- NVMe or PCIe-heavy designs: only two PCIe 2.1 x1 root ports, each shared with SATA (and one with USB3)
- Designs needing more than 16 GB DRAM or more than 32-bit memory bandwidth
- H.265 encode above 4K60, or AV1 encode (the encoder does H.264 and H.265 only)
- Products that need the NPU under mainline Linux today: no RK3576 NPU node upstream as of 7.3-rc7
- Native 2.5 GbE or 10 GbE without a PCIe or USB bridge (GMACs are RGMII/RMII only)
Cost and constraints
- BOM is driven by LPDDR4X/LPDDR5 (two x16 channels on one 32-bit device) and the RK806S-5 PMIC that every vendor schematic opened uses
- FCCSP698L, 16.1 x 17.2 mm, with mixed 0.55/0.60/0.65 mm ball pitch: fanout sets the layer count and via technology
- Commercial RK3576 is rated 0 to 80 C ambient; -40 to 85 C designs need the RK3576J (or the automotive RK3576M), which run lower clocks and drop LPDDR5X
- High-speed lanes are combo PHYs: picking SATA, PCIe or USB3 on each lane is a board-level decision
Inside the RK3576
Drawn by Groundplane from the datasheet rev 1.5. Not Rockchip artwork.
- LPDDR4/4X-4266
- LPDDR5/5X-5500
- 2 ch x16, 16 GB max
- UFS 2.0 2-lane
- eMMC 5.1
- SD 3.0
- FSPI NOR/NAND
- 4x Cortex-A72, 1 MB L2
- 4x Cortex-A53, 512 kB L2
- Cortex-M0 MCU
- Mali-G52 MC3
- RGA 2.5 dual core (2D)
- RKNN dual core, 6 TOPS INT8
- 1 MB NPU SRAM
- Decoder: H.265/VP9/AV1/AVS2 8K30
- Encoder: H.264/H.265 4K60
- JPEG encode and decode
- VDPP and VPSS post process
- 16 MP ISP, 120 dB HDR
- VICAP, 5 CSI groups
- VOP: 3 video ports
- VP0 4K120, VP1 2560x1600, VP2 1080p
- 2x 16-bit LPDDR4/4X/5/5X
- 512 kB system SRAM
- Crypto engine and key ladder
- Secure OTP, TrustZone
- PMU, 12 PLLs, CRU
- Timers, watchdogs, DMAC x3
- 6-ch TSADC, 8-ch SARADC
- PCIe 2.1 x1 / SATA 3
- PCIe 2.1 x1 / SATA 3 / USB3
- USB 3.2 Gen1 + DP 1.4 (USB-C)
- 2x RGMII/RMII GMAC
- SDIO 3.0
- HDMI 2.1 / eDP 1.3
- MIPI DSI-2 (D/C-PHY)
- Parallel RGB, EBC
- 2x CSI-2 D-PHY 4-lane
- CSI-2 D/C-PHY 4-lane
- DVP 16-bit
- 2x CAN
- 12x UART
- 10x I2C, 2x I3C
- 5x SPI
- 5x SAI, 2x PDM, SPDIF
- DSMC, FlexBus
Read from the documents
Each value names the document it was read from.
| CPU | 4x Cortex-A72 up to 2.2 GHz (1 MB L2) + 4x Cortex-A53 up to 2.0 GHz (512 kB L2), plus a Cortex-M0 MCU | Datasheet Rev 1.5, 1.2.1, 1.2.3, Table 3-2 |
|---|---|---|
| GPU | Arm Mali-G52 MC3, up to 900 MHz; OpenGL ES 3.2, Vulkan 1.1, OpenCL 2.0 | Datasheet Rev 1.5, 1.2.6, Table 3-2 |
| NPU | 6 TOPS INT8 (with sparsity), dual core, 1 MB SRAM, INT4/INT8/INT16/FP16/BF16/TF32, up to 950 MHz | Datasheet Rev 1.5, 1.2.5, Table 3-2 |
| Video decode | H.265, VP9, AV1, AVS2 up to 8K30 or 4K120; H.264 up to 4K60 (Main10 profile listed) | Datasheet Rev 1.5, 1.2.4 |
| Video encode | H.264 High and H.265 Main up to 4K60; JPEG/MJPEG up to 4K60 | Datasheet Rev 1.5, 1.2.4 |
| Memory | LPDDR4/LPDDR4X-4266, LPDDR5/LPDDR5X-5500; 2 channels x 16-bit, up to 2 ranks each, 16 GB address space | Datasheet Rev 1.5, 1.2.2 |
| Storage | UFS 2.0 (2 lanes, HS-G3), eMMC 5.1 HS400, SD 3.0, FSPI NOR/NAND (2 chip selects) | Datasheet Rev 1.5, 1.2.2 |
| Display | 3 video ports: VP0 4K120 10-bit, VP1 2560x1600@60 10-bit, VP2 1920x1080@60 8-bit. HDMI 2.1 / eDP 1.3 combo TX, DP 1.4 (USB-C alt mode, MST 3 displays), MIPI DSI-2 (4-lane D-PHY 2.5 Gbps or 3-trio C-PHY), parallel RGB, E-ink EBC | Datasheet Rev 1.5, 1.2.10, 1.2.11 |
| Camera | 3 MIPI CSI-2 inputs: two 4-lane D-PHY 1.2 (each splittable 2x2), one 4-lane D-PHY 2.0 (4.5 Gbps) or 3-trio C-PHY 1.1; DVP 8/10/12/16-bit; 16 MP ISP with 120 dB HDR | Datasheet Rev 1.5, 1.2.7, 1.2.8 |
| PCIe | 2x PCIe 2.1 x1, root complex only, 5 GT/s; lane 0 shared with SATA, lane 1 shared with SATA and USB 3.2 Gen1 | Datasheet Rev 1.5, 1.2.13 |
| USB | USB 3.2 Gen1x1 DRD on the USBDP combo PHY (with DP alt mode) plus a second USB 3.2 Gen1 on the PCIe/SATA combo lane; USB 2.0 OTG | Datasheet Rev 1.5, 1.2.11, 1.2.13 |
| Ethernet | 2x GMAC, 10/100/1000, RGMII or RMII | Datasheet Rev 1.5, 1.2.13 |
| SATA | SATA 3.1 (6 Gb/s, AHCI 1.3.1, eSATA) on either combo lane | Datasheet Rev 1.5, 1.2.13 |
| Other I/O | 2x CAN (ISO 11898-1:2003; Rev 1.5 said CAN FD), 12x UART, 10x I2C, 2x I3C, 5x SPI, 16x PWM, 8-ch 12-bit SARADC, 5x SAI, 2x SPDIF TX/RX, 2x PDM, DSMC, FlexBus, SDIO 3.0 | Datasheet Rev 1.6, 1.2.12 to 1.2.14 |
| Security | TrustZone, crypto engine (AES, SM4, SHA-2, RSA-4096, ECC, SM2), key ladder, secure OTP, DDR scrambling | Datasheet Rev 1.5, 1.2.3 |
| Package | FCCSP698L, 16.1 x 17.2 mm, 698 balls, mixed 0.55/0.60/0.65 mm pitch, MSL 3 | Datasheet Rev 1.5, 1.2.14, 2.4 |
| Temperature | 0 to 80 C ambient (RK3576), Tj max 125 C; theta JA 15.84 C/W, theta JB 6.96 C/W, theta JC 0.67 C/W | Datasheet Rev 1.5, Table 3-1, 3-2, 4-1 |
Variants
| RK3576 | Commercial grade, 0 to 80 C ambient. A72 2.2 GHz, A53 2.0 GHz, GPU 900 MHz, NPU 950 MHz. LPDDR5X-5500 supported. | Datasheet Rev 1.5 |
|---|---|---|
| RK3576-D | Same package and features as RK3576, with the Dolby function (order information only; no other differences listed). | Datasheet Rev 1.5 |
| RK3576J | Industrial grade, -40 to 85 C ambient. Normal mode: A72 1.6 GHz, A53 1.4 GHz, GPU 700 MHz, NPU 700 MHz. Overdrive: A72 2.1 GHz, A53 1.9 GHz, GPU 800 MHz, NPU 850 MHz (the datasheet warns that long overdrive use, especially hot, may shorten lifetime). Memory LPDDR4/LPDDR4X-4266 and LPDDR5-4800; no LPDDR5X. | Datasheet Rev 1.1 |
| RK3576M | Automotive part ("for automobile applications"), -40 to 85 C ambient. A72 2.1 GHz, A53 1.9 GHz, GPU 800 MHz, NPU 850 MHz. LPDDR4/LPDDR4X-4266 and LPDDR5-4800; no LPDDR5X. Same 6 TOPS NPU and 8K30 decode. | Datasheet Rev 1.0 |
| RK3576S | Cut-down part in the same FCCSP698L package: 3 TOPS NPU, decode up to 4K60, H.264/H.265 encode up to 4K30, one PCIe 2.1 x1 lane and one USB 3.0 DRD; no GMAC, SATA or CAN listed and only Video Port0 described. Clocks as RK3576 (A72 2.2 GHz, A53 2.0 GHz), 0 to 80 C. LPDDR4/LPDDR4X-4266 and LPDDR5/5X-4800. | Datasheet Rev 1.2 |
What to watch when you design with it
Size a heatsink for the RK3576 with its datasheet θJC and Tj max filled in, and download the STEP.
Power and PMIC
Every RK3576 schematic opened pairs the SoC with a single RK806S-5 PMIC: Radxa ROCK 4D, the Seeed reComputer RK3576 module, and the Neardi LCH3576 module notes. The datasheet splits the core into separate rails: CPU_BIG_DVDD and CPU_LIT_DVDD (0.75 V typical), GPU_DVDD, NPU_DVDD, LOGIC_DVDD and LOGIC_MEM_DVDD, plus 0.75/0.85/1.8 V PHY rails and VCCIO0 to VCCIO7 IO domains. Neardi notes I2C1 is reserved for the PMIC and that RK806S-5 DC_PWR_ON needs an RC delay for auto power-on. The RK806 datasheet on LCSC covers RK806-1/-2/-3; the RK806S-5 power sequence is in the separate RK806S datasheet (Rev 1.5).
Sources: Datasheet Rev 1.5, Board schematic V1.12, Board schematic v1.0, wiki.neardi.net, PMIC Rev 1.3, PMIC Rev 1.5
DDR
Two 16-bit channels, up to 2 ranks each, 16 GB address space: in practice one 32-bit LPDDR4/4X/5/5X device. LPDDR4/4X runs to 4266 and LPDDR5/5X to 5500 per the datasheet. DDR IO supplies are 1.1 V (LPDDR4/4X) or 1.05 V (LPDDR5/5X) for VDDQ, and 0.6 V or 0.5 V for the DDR PHY digital rail, so the PMIC rail settings follow the DRAM type. ROCK 4D uses LPDDR5. Mainline U-Boot still loads a binary DDR init blob from rkbin (rk3576_ddr_lp4_2112MHz_lp5_2736MHz in the docs example).
Sources: Datasheet Rev 1.5, Board schematic V1.12, docs.u-boot.org
High-speed interfaces
Both PCIe lanes are combo PHYs: lane 0 is PCIe 2.1 or SATA, lane 1 is PCIe 2.1, SATA or USB 3.2 Gen1. The datasheet notes the paired USB 2.0 port is disabled when that USB3 lane is disabled, and PCIe is root complex only. DP 1.4 shares the USBDP PHY with the other USB3 port. Neardi notes: AC-coupling caps on USB3 SSTX, cross TX and RX for M.2 PCIe, D/C-PHY TX and RX must both run D-PHY or both C-PHY, and the C/D-PHY CSI port does not split 2+2 (the two D-PHY CSI ports do).
Sources: Datasheet Rev 1.5, wiki.neardi.net
Boot and maskrom
BootROM boots from FSPI, eMMC, UFS, SD or USB, and accepts code download over USB OTG. Boot order is set by a resistor divider on the SARADC_IN0_BOOT pin: Neardi uses 10k up and 88.7k down for eMMC, then SDMMC0, then USB. Radxa ROCK 4D wires its Maskrom key to pull SARADC_VIN0_BOOT low. Neardi says to keep USB2 OTG0 available for firmware download.
Sources: Datasheet Rev 1.5, Board schematic V1.12, wiki.neardi.net
Thermal
Tj max 125 C. Package theta JA 15.84 C/W (JEDEC 2s2p, natural convection), theta JB 6.96 C/W, theta JC 0.67 C/W. Commercial parts are rated 0 to 80 C ambient. Six TSADC channels, -40 to 125 C, can trigger alarm interrupts and a hardware reset.
Sources: Datasheet Rev 1.5
Gotchas
CAN: datasheet Rev 1.5 and the brief say CAN FD, but Rev 1.6 (2025-09-30) and the RK3576J and RK3576M datasheets describe plain ISO 11898-1:2003 CAN, so confirm CAN FD with Rockchip before relying on it. Clocks vary by vendor page (several SoM vendors list the A53 at 1.8 GHz; the datasheet says 2.0 GHz). The VOP scales only 1/4 to 8x, and the datasheet recommends the RGA for scaling at 4K120. VCCIO domains are 1.8/3.3 V or 1.2/1.8 V and must match the attached peripherals.
Sources: Datasheet Rev 1.5, Datasheet Rev 1.6, Datasheet Rev 1.1, Datasheet Rev 1.0, Product brief V1.2
Layout guides for the RK3576's interfaces
Public layout guidance for each interface this chip has, from vendors who publish it, plus our calculators.
LPDDR4
Point-to-point routing; TI notes that on-die termination on both ends means no board termination is needed. Byte lanes length-matched to their strobe and command/address matched to the clock, all over a solid reference plane. Impedance targets differ by vendor: TI AM62x and ADI EE-480 use 40 ohm single-ended and 80 ohm differential, Synaptics SL1680 uses 50 and 85 ohm, AMD Versal 45 and 82 ohm. Use the SoC vendor's own target and simulate.
- AM62x, AM62Lx DDR Board Design and Layout GuidelinesTexas Instruments, SPRAD06, C, 2025
- AM62Ax, AM62Px, AM62Dx LPDDR4 Board Design and Layout GuidelinesTexas Instruments, SPRAD66, B, 2024
- ADSP-2184x/ADSP-SC84x LPDDR4 Board Design GuidelinesAnalog Devices, EE-480, 1, 2026
- SL1680 General PCB Design and LPDDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001390-01, E
- DDR length matching calculatorGroundplane calculator
LPDDR4X
Same topology and matching discipline as LPDDR4, with a lower I/O voltage, so routing rules are usually published for both together. Synaptics SL1680 gives 50 ohm single-ended and 85 ohm differential for LPDDR4 and LPDDR4X; AMD Versal gives 45 and 82 ohm. Check the SoC vendor target before fixing the stackup.
- SL1680 General PCB Design and LPDDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001390-01, E
- SL1640 General PCB Design and DDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001529-01, D
- Versal Adaptive SoC PCB Design User Guide: PCB Routing Guidelines for LPDDR4/4x InterfacesAMD, UG863, 1.12, 2026
- DDR length matching calculatorGroundplane calculator
LPDDR5
LPDDR5 replaces the bidirectional strobe with a write clock (WCK) and an optional read strobe, so clock routing and skew budgets change from LPDDR4. AMD Versal specifies 40 ohm single-ended for command/address and data and 75 ohm differential for the clocks and read strobe.
- Versal Adaptive SoC PCB Design User Guide: PCB Routing Guidelines for LPDDR5/5x InterfacesAMD, UG863, 1.12, 2026
- PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex 5 FPGAs and SoCsAltera, 821801, 2026
- DDR length matching calculatorGroundplane calculator
eMMC
A single-ended bus: CLK, CMD, DAT0 to DAT7 and, for HS400, the data strobe. TI and Synaptics both route it at 50 ohm single-ended, match the group, and keep stubs short; Synaptics places a 22 or 33 ohm series resistor on CLK and STRB. At HS400 TI also checks the eMMC I/O supply impedance, not just the traces.
- AM62Px eMMC HS400 Board Design and Simulation GuidelinesTexas Instruments, SPRADP5, A, 2026
- Astra Machina Foundation Series eMMC ConfigurationSynaptics, PN 506-001594-01, D
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
SD card / SDIO
Single-ended CLK, CMD and four data lines over a solid ground plane, at constant trace width and matched length. NXP asks for clock-to-neighbor spacing greater than twice the trace height above the plane and 1.5 times for data and CMD, with 45 degree bends. UHS modes switch the I/O to 1.8 V, so a level translator often sits next to the socket.
- NVT4557/NVT4558/NVT4858 voltage-level translator layout guidelineNXP, AN13158, 1.1, 2022
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
- SD Physical Layer Simplified SpecificationSD Association, 9.10, 2023
UFS
UFS runs over MIPI M-PHY differential lanes, so it is routed like any multi-gigabit serial link: tight intra-pair matching, minimal vias and stubs, continuous reference planes. TI specifies 100 ohm differential for UFS lanes on Jacinto 7 and requires simulation against its channel limits.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
PCIe
AC-coupled differential lanes routed with no stubs, minimal vias and back-drilled or blind vias where speed demands, with lane-to-lane skew handled by the receiver. Targets differ by guide: TI Jacinto 7 uses 85 ohm differential for lanes and 100 ohm for the reference clock, while TI's earlier SoC guide tabulates 100 ohm and, for some devices, 95 ohm. Match the target to your connector and stackup.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
USB 3.x
SuperSpeed TX and RX pairs are routed at 90 ohm differential in all three TI guides (SPRAAR7 lists 95 ohm for some devices), with AC coupling capacitors on TX, symmetric pad and via placement, and matched via counts within each pair. Keep the pairs away from the USB 2.0 pair and other aggressors, and place ESD at the connector.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
USB 2.0
One D+/D- pair at 90 ohm differential, routed in parallel for its whole length with minimal deviations at the connector and package. NXP keeps clocks and periodic signals at least 50 mils away and other signals at least 20 mils away from the pair.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
HDMI
Four TMDS pairs (three data, one clock) at 100 ohm differential, as both TI guides state, with tight intra-pair matching and as few vias as possible between the SoC and the connector. HDMI also needs 5 V supply switching, DDC and CEC level handling, hot-plug detect and ESD at the connector.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- TPD12S016 PCB Layout Guidelines for HDMI ESDTexas Instruments, SLLA324, 2012
DisplayPort / eDP
Main-link lanes are routed at 100 ohm differential in both TI guides, with no stubs and few vias; TI Jacinto 7 allows 2 vias per trace. When DisplayPort shares a USB-C connector through alt mode, the lanes run through the Type-C mux and the SuperSpeed rules apply to the shared path.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
MIPI DSI
MIPI D-PHY clock and data lanes are routed as 100 ohm differential pairs over a solid reference; TI Jacinto 7 allows no stubs, 2 vias per trace and 40 ps lane-to-lane skew. Connectors and flex cables to the panel are usually the largest discontinuity, so keep the board segment short and clean.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex 5 FPGAs and SoCsAltera, 821801, 2026
MIPI CSI-2
Same D-PHY rules as DSI: 100 ohm differential lanes in both TI guides, with lane-to-lane skew bounded (40 ps in TI Jacinto 7). Size the lane count and lane rate from the sensor's output format before routing.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex 5 FPGAs and SoCsAltera, 821801, 2026
- MIPI CSI-2 bandwidth calculatorGroundplane calculator
Ethernet (RGMII / RMII)
TI routes MAC-to-PHY (MII family) traces at 50 ohm single-ended, under 6 inches, matched within 20 mils for gigabit, and the PHY-side MDI pairs at 100 ohm differential. RGMII also needs a 1.5 to 2.0 ns clock-to-data delay, added on the board or inside the MAC or PHY (RGMII-ID); decide which before layout so it is not applied twice.
- Ethernet PHY PCB Design Layout ChecklistTexas Instruments, SNLA387, 2021
- PCB Design Guideline for RGMII InterfaceRenesas, R01AN6272EJ0141, 1.41, 2026
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
SATA
AC-coupled TX and RX pairs at 100 ohm differential in TI's SoC guide, routed with the same via, stub and reference plane rules as PCIe and USB 3. On Rockchip parts SATA usually shares a combo PHY with PCIe or USB 3, so the lane is routed once to whichever connector the design picks.
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
Board-level design guides
Impedance and timing, power, thermal and ESD guidance that applies to any board around this chip.
Impedance and timing
Every high-speed interface on the board comes down to the same two numbers: the trace impedance your stackup actually gives, and the delay each trace adds. Set the stackup with your fab first, then route to its impedance table and match lengths in time, not millimeters, where the layers differ.
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- PCB impedance calculatorGroundplane calculator
- PCB propagation delay calculatorGroundplane calculator
Power delivery
For each switching regulator, place and route the input capacitor first, keep the switching current loop small, and keep the switch node short. Give the SoC rails solid planes and decoupling at the balls, and size current-carrying copper and vias for the real load.
- Five steps to a great PCB layout for a step-down converterTexas Instruments, SLYT614, 2015
- AN-1149 Layout Guidelines for Switching Power SuppliesTexas Instruments, SNVA021, C, 2013
- AN-1229 SIMPLE SWITCHER PCB Layout GuidelinesTexas Instruments, SNVA054, C, 2013
- Buck converter calculatorGroundplane calculator
- LDO power dissipation calculatorGroundplane calculator
- PCB trace width calculatorGroundplane calculator
- Via current calculatorGroundplane calculator
Thermal
Theta-JA is measured on a JEDEC test board that carries most of the heat, so it does not transfer directly to a product board; use it to compare packages and use the psi metrics for estimates. Thermal vias under the package, copper area and copper thickness move the most heat into the board.
- Semiconductor and IC Package Thermal MetricsTexas Instruments, SPRA953, D, 2024
- AN-2020 Thermal Design By Insight, Not HindsightTexas Instruments, SNVA419, C, 2013
- Heatsink thermal resistance calculatorGroundplane calculator
- LDO power dissipation calculatorGroundplane calculator
ESD protection
Place the TVS as close to the connector as design rules allow, route from the connector to the TVS with no stub, and keep the protected IC further from the TVS than the TVS is from the connector. Choose parts by clamping performance and by capacitance low enough for the interface speed.
- ESD Protection Layout GuideTexas Instruments, SLVA680, A, 2022
- Reading and Understanding an ESD Protection Data SheetTexas Instruments, SLLA305, A
- TPD12S016 PCB Layout Guidelines for HDMI ESDTexas Instruments, SLLA324, 2012
- PCB conductor spacing calculator (IPC-2221)Groundplane calculator
Rockchip's hardware design guide
Rockchip's hardware design guide, EVB reference schematics and DDR templates come from Rockchip or an authorized agent, usually under NDA, or through your SoM vendor. We do not link copies circulating elsewhere. The vendor schematics and open designs on the Boards tab are real, shipped layouts on the RK3576 and the best public reference.
BSP, mainline and toolkits
| Area | Status | Links |
|---|---|---|
| Vendor BSP kernel | Rockchip ships RK3576 in its 6.1 BSP (rockchip-linux/kernel develop-6.1, last commit 2026-07-29), and the rk3576.dtsi is also present in develop-6.6 and develop-6.12 branches. Board vendors ship 6.1 based kernels (Forlinx lists Linux 6.1.57 and 6.1.118).Checked 2026-10-13 | |
| Mainline Linux | rk3576.dtsi landed in 6.13 with CPU, clocks, pinctrl, eMMC/SD, GMAC, I2C, SPI, UART, SARADC and the Mali-G52 GPU node (Panfrost, arm,mali-bifrost). 6.14: USB3 (DWC3), USBDP and combo PHYs. 6.15: VOP2 display, HDMI TX, IOMMU, UFS host, OTP. 6.16: PCIe, SATA, SAI audio, RNG. 6.18: MIPI DSI-2, MIPI DC-PHY, thermal (TSADC). 7.0: VDPU383 video decoder (H.264 and H.265). 7.1: DisplayPort and SPDIF. 7.3-rc7: eDP. Not in the mainline dtsi as of 7.3-rc7: NPU (no RK3576 compatible in the rocket NPU binding), CAN, ISP/VICAP camera path, video encoder, RGA.Checked 2026-10-13 | |
| Mainline board support | Board device trees in mainline as of 7.3-rc7: ArmSoM Sige5 (6.13), Rockchip EVB1 (6.14), Firefly ROC-RK3576-PC and Radxa ROCK 4D (6.15), Luckfox Omni3576 and FriendlyELEC NanoPi M5 (6.17), 100ask DshanPi A1 and NanoPi R76S (6.19), Rockchip EVB2 and Khadas Edge 2L (7.1), ArmSoM CM5-IO, LCKFB TSPI-3M and Anbernic RG Vita Pro (7.3-rc7).Checked 2026-10-13 | |
| U-Boot and TF-A | Mainline U-Boot added RK3576 in v2025.07 (ROC-RK3576-PC defconfig); v2025.10 added the generic and Sige5 configs; v2026.01 added ROCK 4D, NanoPi M5 and Omni3576; v2026.07 added NanoPi R76S. Mainline TF-A has plat/rockchip/rk3576 from v2.13.0 (first commit 2025-02-24). The U-Boot docs build example still uses the rkbin BL31 and DDR init binaries. Collabora (May 2026) says the DDR trainer is the last binary blob in the boot chain; Flipper says OP-TEE has no RK3576 support.Checked 2026-10-13 | |
| NPU toolkit | RKNN-Toolkit2 lists the RK3576 series as a supported platform; the repo README is at v2.5.0 (commit 2026-10-13), latest tagged GitHub release v2.3.2 (2025-04-09). RKNN-LLM lists RK3576 and is at release v1.3.1 (2026-09-29). NPU use requires the vendor kernel; the mainline rocket driver does not cover RK3576 yet.Checked 2026-10-13 | |
| Video (MPP) and 2D (RGA) | Vendor userspace is Rockchip MPP for encode and decode and librga for the dual-core RGA 2.5, on the BSP kernel. On mainline, the VDPU383 decoder uses the V4L2 stateless API, with userspace in GStreamer 1.28 per CNX; encode has no mainline driver yet.Checked 2026-10-13 | |
| Distributions | Armbian has RK3576 board configs including ROCK 4D, Radxa CM4 IO, NanoPi M5, NanoPi R76S, Banana Pi M5 Pro, reComputer RK3576 (supported, .conf) and Sige5, ArmSoM CM5 IO, DshanPi A1, LubanCat 3 (community, .csc). OpenWrt 25.12.5 has images for ROCK 4D and NanoPi R76S. Joshua Riek ubuntu-rockchip (archived) includes an ArmSoM Sige5 config. Radxa publishes Debian (RSDK) and Android 14 images for ROCK 4D.Checked 2026-10-13 |
RK3576 on GitHub
Repositories for this chip: vendor code, mainline work, toolkits, distributions and open hardware.
- Vendor BSPfriendlyarm/sd-fuse_rk3576FriendlyELEC SD image builder for its RK3576 boards; pairs with kernel-rockchip branch nanopi6-v6.1.y and uboot-rockchip nanopi6-v2017.09. Last commit 2026-09.
- Vendor BSPLuckfoxTECH/Luckfox-Omni3576-docsLuckfox documentation for the Core3576 module and Omni3576 carrier, with pinout spreadsheet, module design guide, schematic PDF and STEP models. Last commit 2026-07.
- Kernelrockchip-linux/kernelRockchip BSP kernel; RK3576 first appears on develop-6.1 and continues on develop-6.6 and develop-6.12, there is no 5.10 support. Last commit 2026-08.
- Kernelradxa/kernelRadxa BSP kernel; branch linux-6.1-stan-rkr4.1 supports ROCK 4D and the CM4 and NX4 RK3576 modules. Last commit 2026-10.
- Kerneltorvalds/linuxMainline Linux carries rk3576.dtsi and about 19 board device trees for RK3576. Last commit 2026-10.
- Bootloaderrockchip-linux/u-bootRockchip U-Boot; next-dev carries the RK3576 SoC code under arch/arm/mach-rockchip/rk3576. Last commit 2026-08.
- Bootloaderrockchip-linux/rkbinClosed DDR init, loaders and BL31; bin/rk35 has the rk3576 DDR, SPL and BL31 binaries, the largest set of any chip in the folder. Last commit 2026-08.
- Bootloaderu-boot/u-bootMainline U-Boot includes generic-rk3576_defconfig plus NanoPi M5 and R76S board configs. Last commit 2026-10.
- BootloaderTrustedFirmware-A/trusted-firmware-aRead-only mirror of TF-A; plat/rockchip/rk3576 provides an open BL31 for mainline boot chains. Last commit 2026-10.
- Bootloadergahingwoo/edk2-rk3576Community EDK2 UEFI firmware port for RK3576 devices. Last commit 2026-10.
- NPUairockchip/rknn-toolkit2RKNN-Toolkit2 converter and RKNPU2 runtime; RK3576 is listed as a supported platform for its 6 TOPS two core NPU. Last commit 2026-10.
- NPUairockchip/rknn-llmRKLLM toolkit and runtime; RK3576 is one of four supported platforms for on device LLM and VLM inference. Last commit 2026-09.
- NPUairockchip/rknn_model_zooReference model conversions and demos; every vision model in the table lists RK3576 as supported. Last commit 2026-10.
- Mediarockchip-linux/mppMedia Process Platform; the SoC table in osal/mpp_soc.c includes rk3576 and its VDPU383 decoder. Last commit 2026-09.
- Mediaairockchip/librgaRGA 2D acceleration library with RK3576 in its supported chip list. Last commit 2026-06.
- Distributionarmbian/buildArmbian build framework with RK3576 boards such as ArmSoM Sige5, Banana Pi M5 Pro and NanoPi M5 in the rk35xx family. Last commit 2026-10.
- DistributionROCKNIX/distributionHandheld gaming distribution with an RK3576 device tree in projects/ROCKNIX/devices. Last commit 2026-10.
- Distributionopenwrt/openwrtOpenWrt rockchip/armv8 target builds images for NanoPi M5, NanoPi R76S and ROCK 4D on RK3576. Last commit 2026-10.
- Open hardwarejoengineer656/RK3576-SBCv2Open source RK3576 single board computer drawn in KiCad 10, with schematic sheets and board layout in the repo. Last commit 2026-10.
- Toolsrockchip-linux/rkdeveloptoolRockchip open source USB flashing tool for maskrom and loader mode, the Linux and macOS alternative to RKDevTool. Last commit 2025-03.
RK3576 system on modules
Any of these can sit on a carrier board we design.
| Module | Vendor | Connector | RAM | Design files | Price | Buy |
|---|---|---|---|---|---|---|
| CM4 (RK3576) | Radxa | 3x 100-pin 0.4 mm board-to-board | up to 16 GB LPDDR4X | module schematic PDF, placement PDF, pinout XLSX, 2D DXF, 3D STEP | ||
| NX4 | Radxa | 260-pin SO-DIMM edge | up to 16 GB LPDDR5 | module schematic PDF, placement PDF, pinout XLSX, DXF, STEP | ||
| Core-3576JD4 | Firefly | 260-pin SO-DIMM-style edge, 0.5 mm pitch | 4 to 16 GB LPDDR4, LPDDR4X or LPDDR5 | none | USD 189, 4 GB / 32 GB (Firefly store) | |
| iCore-3576Q | Firefly | board-to-board, 2x 80-pin + 2x 100-pin | 2 to 8 GB LPDDR4, LPDDR4X or LPDDR5 | none | USD 149, 2 GB / 32 GB module (Firefly store) | |
| CM5 (RK3576) | ArmSoM | board-to-board, Raspberry Pi CM4 footprint (vendor says CM4 baseboards work, with 1 HDMI and 1 DSI) | 2 to 16 GB LPDDR5 | schematic PDF, DXF, 3D STEP, pin list and CM4/CM5 pin comparison XLSX | USD 140, 4 GB / 64 GB with Wi-Fi (ArmSoM store) | |
| AIM5 | ArmSoM | 260-pin edge (vendor claims Jetson Nano and TX2 pin compatibility) | 8 or 16 GB | schematic and 2D (Baidu Pan) | ||
| BPI-CM5 Pro | Banana Pi | board-to-board, Raspberry Pi CM4 baseboard compatible per vendor | 4 to 16 GB LPDDR5 | module schematic and 2D zip; IO board schematic, 2D and placement zip | USD 154, 4 GB / 32 GB without Wi-Fi (BPI shop) | |
| Core3576 | Luckfox | 260-pin SO-DIMM edge | 4 or 8 GB LPDDR4X | DWG drawing, 3D STEP and pinout XLSX (no module schematic) | from USD 119.99 (Luckfox store) | |
| reComputer RK3576 Module | Seeed Studio | 2x 100-pin board-to-board (listed as fitting the Raspberry Pi CM4 IO Board) | 4 or 8 GB LPDDR5 | module schematic PDF | ||
| FET3576-C | Forlinx | 4x 100-pin 0.4 mm board-to-board | 2 or 4 GB LPDDR4 | carrier schematic, carrier PCB and SoM pinmux listed (access terms not stated) | ||
| MYC-LR3576 | MYIR | 381-pin LGA | 4 or 8 GB LPDDR4X | STEP; schematic PDFs mentioned under development resources | USD 122, 4 GB / 32 GB sample price (MYIR) | |
| CM3576 | Boardcon | 218-pin edge pads, 0.9 mm pitch (QFN-style) | 4 or 8 GB | hardware manual, 3D model | ||
| LGA3576 | Boardcon | LGA, 1.25 mm ball pitch (vendor lists the package as LAG330) | 4 or 8 GB LPDDR5 | hardware manual, 3D model | ||
| MINI3576 | Boardcon | 2x 100-pin + 1x 44-pin 0.4 mm board-to-board | 4 or 8 GB | hardware manual, connector datasheet, 3D model | ||
| SOM-3576 | Geniatech | MXM 3.0, 314-pin edge | up to 16 GB |
Every public RK3576 board
| Board | Vendor | Type | RAM | Notable I/O | Design files | Price | Buy |
|---|---|---|---|---|---|---|---|
| ROCK 4D | Radxa | SBC, 85 x 56 mm | 2 to 16 GB LPDDR5 | HDMI 2.1 4K120, 4-lane MIPI DSI, PCIe 2.1 x1 via FPC, GbE (PoE via HAT), Wi-Fi 6, eMMC and UFS module sockets, RK3576 or RK3576J | schematic PDF, placement PDF, 2D DXF, 3D STEP | ||
| CM4 IO Board | Radxa | Carrier | M.2 M-key 2280 NVMe, UFS module slot, GbE with PoE, microSD, 40-pin header, 12 V DC | full Altium schematic and layout on GitHub, plus PDF, DXF, STEP, BOM | |||
| NX4 IO Board | Radxa | Carrier | full Altium schematic and layout on GitHub, plus PDF, DXF, STEP | ||||
| NanoPi M5 | FriendlyELEC | SBC, 90 x 62 mm, 8-layer | 3 to 16 GB LPDDR4X or LPDDR5 | 2x GbE, 2x USB 3.2 Gen1, M.2 M-key PCIe 2.1 x1, HDMI, 2x 4-lane CSI, 4-lane DSI, UFS 2.0 module socket, USB-C PD 6 to 20 V | schematic PDF (LPDDR4X and LPDDR5 versions), DXF | USD 75, 3 GB (FriendlyELEC store) | |
| NanoPi R76S | FriendlyELEC | SBC, 58 x 58 mm router, 8-layer | 2 to 4 GB LPDDR4X (LPDDR5 schematic also published) | 2x 2.5 GbE (over PCIe), USB 3.2 Gen1, HDMI 2.0, M.2 SDIO Wi-Fi, USB-C 5 V | schematic PDF (LPDDR4X and LPDDR5 versions), DXF | USD 75, 3 GB without eMMC (FriendlyELEC store) | |
| ROC-RK3576-PC | Firefly | SBC, 93 x 60 mm | 4 to 16 GB LPDDR4 or LPDDR5 | GbE, Wi-Fi, BT 5.0, HDMI 2.1, DP 1.4, DSI, M.2 2242 PCIe/SATA, DC 12 to 24 V | none (download page lists firmware, SDK and tools only) | USD 259, 4 GB / 64 GB (Firefly store) | |
| AIO-3576JD4 | Firefly | SBC, 122.9 x 85 mm | 2x GbE, Wi-Fi 6, BT 5.2, 4G/5G | none | USD 249, 4 GB / 32 GB (Firefly store) | ||
| Sige5 | ArmSoM | SBC, 92 x 62 mm | 4 to 16 GB LPDDR4X | 2x GbE, Wi-Fi 6, BT 5.3, HDMI 2.1, DP 1.4, DSI, 2x 4-lane CSI, M.2 M-key PCIe 2.1 x1, USB-C PD 5 to 23 V | schematic PDF (1V1 to 1V3), placement PDF, DXF | USD 164, 4 GB / 32 GB (ArmSoM store) | |
| CM5-IO | ArmSoM | Carrier, 100 x 80 mm | 4x USB 3.0, HDMI and USB-C DP, GbE with PoE, M.2 M-key NVMe, 40-pin header, 12 V DC | full OrCAD schematic and Allegro layout, plus PDF, placement and DXF | USD 36 (ArmSoM store, option on the CM5 page) | ||
| BPI-M5 Pro | Banana Pi | SBC, 92 x 62 mm | 4 to 16 GB LPDDR4X | 2x GbE, HDMI 2.1, DP 1.4, DSI, M.2 M-key PCIe x1, Wi-Fi 6, USB-C PD | schematic, placement and DXF | USD 164, 4 GB / 32 GB (BPI shop) | |
| Omni3576 | Luckfox | Dev kit, Core3576 on a base board | 4 or 8 GB LPDDR4X | 2x GbE, PoE 802.3af, HDMI 2.1, USB-C DP, M.2 M-key NVMe, Wi-Fi 6, BT, 2x 4-lane CSI | base board schematic PDF, DWG, STEP (GitHub, no license) | from USD 129.99 (Luckfox store) | |
| reComputer RK3576-20 | Seeed Studio | SBC, AI box with enclosure | 4 to 16 GB LPDDR5 | 2x GbE (one PoE PD), M.2 M-key PCIe 2.1 x1, miniPCIe for LTE or LoRaWAN, HDMI, USB-C OTG with DP, MaskROM button | schematic PDF, enclosure STEP | USD 159, 4 GB (Seeed store) | |
| OK3576-C | Forlinx | Dev kit, FET3576-C on carrier | carrier schematic and PCB listed on the SoM page | ||||
| MYD-LR3576 | MYIR | Dev kit, 90 x 120 mm | HDMI, mini DP, DSI, 3x MIPI CSI, 2x GbE, 2x CAN, M.2 NVMe | USD 169, 4 GB / 32 GB (MYIR) | |||
| EM3576 | Boardcon | Dev kit, 170 x 120 mm, CM3576 on carrier | 4 or 8 GB | 12x AHD camera inputs (BNC), HDMI 2.1, 4-lane DSI, GbE, Wi-Fi, NFC, SATA, M.2, RS485, CAN | hardware manual (no schematic listed) | ||
| Idea3576 | Boardcon | SBC, 155 x 115 mm base board with a 40 x 30 mm CPU module | |||||
| SBC3576 | Boardcon | SBC, 110 x 85 mm | |||||
| Compact3576 | Boardcon | SBC, 152.5 x 83 mm | |||||
| Edge 2L | Khadas | SBC, credit-card size, ultraslim | none available (the hardware docs link schematic, DXF and CAD folders; the schematic file is missing and the folders are empty) | ||||
| RK3576 Evaluation Board (DFR1218) | DFRobot | Dev kit, 146 x 102 mm carrier with core board | 8 GB LPDDR5X | 64 GB eMMC, optional UFS, GbE, CAN FD, RS485, HDMI, DP, CSI, DSI, M.2 B-key and M-key, 12 to 24 V DC | carrier schematic PDF and full KiCad schematic and layout |
Prices and links as checked on the dates in our data; the latest check on this page was 2026-10-13. Amazon links marked * are affiliate links; see our disclosure.
Boards with published design files
| Project | Author | Files | Tool | License |
|---|---|---|---|---|
| DFRobot RK3576 Evaluation Board carrier (DFR1218) | DFRobot | schematic PDF, KiCad 9 project: schematic and 6-layer PCB layout (146 x 102 mm) | KiCad | not stated |
| Radxa CM4 IO Board V1.10 | Radxa | Altium schematic and PCB layout, OrCAD DSN and PADS PCB exports, schematic PDF, BOM, placement map, 2D DXF, 3D STEP | Altium | not stated |
| Radxa NX4 IO Board V1.11 | Radxa | Altium schematic and PCB layout, OrCAD DSN and PADS PCB exports, schematic PDF, placement PDF, DXF, 3D STEP | Altium | not stated |
| ArmSoM CM5-IO 1V1 | ArmSoM | OrCAD DSN schematic, Allegro .brd layout, schematic PDF, placement PDF, DXF | Allegro | not stated |
| RK3576 SBC v2 (work in progress, not fabricated) | joengineer656 | KiCad schematic (chip-down RK3576, LPDDR5, UFS/eMMC), KiCad PCB layout, design rules | KiCad | CERN-OHL-P-2.0 |
| Triangulate AU_01 armband carrier | sandgum | KiCad schematic, KiCad PCB layout, enclosure STEP | KiCad | not stated |
Buying the chip
Order information gives 840 pieces per package quantity (RK3576 and RK3576-D). No public price or source was found for bare RK3576J; industrial designs usually buy it on a SoM (Radxa, Forlinx, MYIR, Boardcon and Firefly list RK3576J modules).
- LCSC
- RK3576 (LCSC C42388007, FCCSP-698L) listed in stock, 291 units, MOQ 1, USD 22.67 at 1+, USD 21.00 at 30+.
- JLCPCB parts library
- Same part (C42388007) listed as an Extended part for assembly, with an EasyEDA symbol and footprint; stock and price not shown on the page.
- Rockchip direct
- The Rockchip contact page lists a sales hotline and regional offices, and names Microtech (Suwon) and InSignal (Seoul) as official distributors for Korea; no other distributor list and no public MOQ for RK3576.
Datasheet, TRM and design documents
Linked where they are publicly hosted; we do not rehost Rockchip documents. These are third-party documents: we are not responsible for their accuracy, availability or confidentiality status. Disclosure.
- DatasheetRK3576 DatasheetRev 1.5 · 2024-12-16 · hosted by FriendlyELEC wiki · checked 2026-10-13
- DatasheetRK3576 DatasheetRev 1.1 · 2024-04-30 · hosted by Luckfox · checked 2026-10-13
- DatasheetRK3576 DatasheetRev 1.0 · 2024-03-15 · hosted by MangoPi · checked 2026-10-13
- Product briefRK3576 Brief DatasheetV1.2 · 2024-03-11 · hosted by Rockchip · checked 2026-10-13
- Product briefRK3576 Brief Datasheet (2025 copyright, no revision printed)hosted by Rockchip · checked 2026-10-13
- Product briefRK3576 product pagehosted by Rockchip · checked 2026-10-13
- Board schematicRadxa ROCK 4D schematic (RK3576, RK806S-5, LPDDR5)V1.12 · hosted by Radxa · checked 2026-10-13
- Board schematicSeeed reComputer RK3576 Module schematicv1.0 · hosted by Seeed Studio · checked 2026-10-13
- Board schematicFriendlyELEC NanoPi M5 schematic (LPDDR5 version)2411 · hosted by FriendlyELEC wiki · checked 2026-10-13
- PMICRK806 Datasheet (RK806-1, -2, -3; the RK806S-5 used with RK3576 is a separate datasheet)Rev 1.3 · 2023-10-19 · hosted by LCSC · checked 2026-10-13
- OtherMYIR MYC-LR3576 / MYC-LR3576J SoM page (RK3576J grade and temperature)hosted by MYIR · checked 2026-10-13
- DatasheetRK3576 DatasheetRev 1.6 · 2025-09-30 · community mirror (rockchip.fr), not hosted by Rockchip · checked 2026-10-13
- DatasheetRK3576J DatasheetRev 1.1 · 2025-09-30 · community mirror (rockchip.fr), not hosted by Rockchip · checked 2026-10-13
- DatasheetRK3576M DatasheetRev 1.0 · 2025-09-24 · community mirror (rockchip.fr), not hosted by Rockchip · checked 2026-10-13
- DatasheetRK3576S DatasheetRev 1.2 · 2025-09-30 · community mirror (rockchip.fr), not hosted by Rockchip · checked 2026-10-13
- TRMRockchip RK3576 TRM Part 1Rev 1.2 · 2024-06-24 · community mirror (rockchip.fr), not hosted by Rockchip · checked 2026-10-13
- TRMRockchip RK3576 TRM Part 2Rev 1.2 · 2024-06-24 · community mirror (rockchip.fr), not hosted by Rockchip · checked 2026-10-13
- PMICRK806S Datasheet (covers RK806S-5 used with RK3576)Rev 1.5 · 2024-07-16 · community mirror (rockchip.fr), not hosted by Rockchip · checked 2026-10-13
Questions about the RK3576
Yes. WarpKVM 01, our 4K KVM, runs on the RK3576 with an RK628H HDMI bridge, on an eight-layer main board we designed. Two rev A boards came up in October 2026, capturing 4K60 over two CSI links.
Rockchip itself hosts only the brief datasheet (V1.2, March 2024) and a product page on rock-chips.com. The full datasheet is published by board vendors: Rev 1.5 (2024-12-16) on the FriendlyELEC wiki, Rev 1.1 on Luckfox, Rev 1.0 on MangoPi. The newest, Rev 1.6 (2025-09-30), the RK3576J, RK3576M and RK3576S datasheets and the TRM Rev 1.2 are only on the community mirror rockchip.fr. The hardware design guide is not linked from any host.
CPU drops from 4x A76 + 4x A55 to 4x A72 + 4x A53. NPU is the same 6 TOPS. GPU is Mali-G52 MC3 instead of G610 MP4. PCIe goes from PCIe 3.0 x4 plus PCIe 2.1 lanes to two PCIe 2.1 x1 lanes, DRAM from 64-bit to 32-bit with a 16 GB address space, decode from 8K60 to 8K30, encode from 8K30 to 4K60. RK3576 adds UFS 2.0 and a C-PHY option on one camera port and on DSI.
A dual-core Rockchip NPU rated 6 TOPS INT8 (with sparsity), supporting INT4, INT8, INT16, FP16, BF16 and TF32, with 1 MB SRAM, at up to 950 MHz. Models are converted with RKNN-Toolkit2 (RK3576 listed) and LLMs with RKNN-LLM, and run on the Rockchip vendor kernel. Mainline Linux has no RK3576 NPU support as of 7.3-rc7.
Mostly. Base support landed in 6.13, USB3 in 6.14, display, HDMI and UFS in 6.15, PCIe and SATA in 6.16, DSI and thermal in 6.18, the H.264/H.265 decoder in 7.0, DisplayPort in 7.1, eDP queued for 7.3 (in 7.3-rc7). Missing as of 7.3-rc7: NPU, video encoder, camera ISP, CAN. Mainline U-Boot supports it from v2025.07 and TF-A from v2.13.0, but the DDR init is still an rkbin blob.
RK3576-D is the RK3576 with the Dolby function, per the datasheet order table. RK3576J is the industrial part, rated -40 to 85 C in its datasheet, with normal-mode clocks of A72 1.6 GHz and A53 1.4 GHz and no LPDDR5X; module vendors price it about 20 to 40 percent above the commercial module (MYIR sample prices USD 122 vs 147 for 4 GB). RK3576M is the automotive part (-40 to 85 C, A72 2.1 GHz). RK3576S is a cut-down part with a 3 TOPS NPU, 4K60 decode, one PCIe lane and no GMAC.
It depends on the connector. CM4-size (55 x 40 mm) B2B: Radxa CM4 (3x 100-pin), ArmSoM CM5 / Banana Pi BPI-CM5 Pro and Seeed reComputer RK3576 module. 260-pin SO-DIMM (69.6 x 45 mm): Radxa NX4, Luckfox Core3576, Firefly Core-3576JD4, ArmSoM AIM5. Solder-down LGA: MYIR MYC-LR3576 (381-pin), Boardcon LGA3576. Radxa (CM4 IO, NX4 IO) and ArmSoM (CM5-IO) publish full carrier layouts to start from.
Related chips and reading
- RK3588 / RK3588SEdge AI boxes, NVR, 8K signage, Arm desktops and servers
- RK3568Routers, NAS, gateways, NVR, industrial HMI
- RK3566HMI, e-ink readers, handhelds, CM4-class SoMs, small routers
- RK3562Cost-down HMI, tablets, industrial gateways
- RK3399Mainline-first products, laptops, NAS, routers, HMI
- RV1126BAI IP cameras, multi-camera vision
We'll design your RK3576 board.
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Links and facts on this page checked 2026-10-13. Spotted something out of date? Tell us through the contact form.
Compiled from publicly available sources: datasheets, technical reference manuals, vendor product pages, schematics and source code published by their owners and third parties. We link to documents where others host them and do not host, endorse or vouch for them. Everything on these pages, including our own specs, summaries, block diagrams, comparisons, calculators and design notes, is for reference only and may contain errors or be out of date. It is provided as is, and Groundplane is not responsible for errors in it, for third-party documents, or for any design, board or decision based on it. Always check the manufacturer's current datasheet, reference manual and design guidance before you design a board. Rockchip, Allwinner, Raspberry Pi and other product names are trademarks of their owners; we are not affiliated with any of them. See our disclosure.