RK3562
Low-cost quad Cortex-A53 SoC with a 1 TOPS NPU, 13 MP ISP and dual CAN in a 13.9 mm FCCSP, but display tops out at 2048x1080, there is no native HDMI, and PCIe and USB 3.0 share one lane.
- CPU
- 4x A53 2.0 GHz
- GPU
- Mali-G52 2EE
- NPU
- 1 TOPS (INT8/INT16/FP16, BF16, TF32)
- Video
- 4K30 H.265/VP9 decode, 1080p60 H.264 encode
- PCIe
- PCIe 2.1 x1 (shared with USB 3.0)
What the RK3562 is for
Right for
- Panel HMIs up to 2048x1080 on MIPI DSI, LVDS or parallel RGB
- Industrial gateways needing 2x CAN, GbE plus 10/100 MAC and many UARTs (up to 10)
- Light edge vision: up to 4 camera sensors through one 13 MP ISP, with small INT8 models on the 1 TOPS NPU
- Wide-temperature designs on the RK3562J (-40 to 85 C ambient)
- Cost-sensitive boards: bare chip listed at USD 8.07 to 11.91 at LCSC (checked 2026-10-13)
Wrong for
- Products needing native HDMI, eDP or 4K display output (a bridge chip is required)
- H.265 encoding or 4K encoding: the encoder is H.264 only, up to 1080p60
- NVMe plus USB 3.0 at once: one Multi-PHY carries either PCIe 2.1 x1 or USB 3.0
- SATA or multi-lane PCIe storage
- Compute-heavy workloads: four in-order Cortex-A53 cores, no big cores
Cost and constraints
- Single display pipeline, max 2048x1080@60; MIPI DSI and LVDS share pins
- One USB 3.0 / PCIe 2.1 x1 Multi-PHY, one USB 2.0 host
- 32-bit DDR interface, 8 GB maximum address space
- RK3562J runs 1.2 GHz in normal mode; 1.8 GHz overdrive is rated with a lifetime penalty
- Mainline Linux (to 7.3-rc7) lacks USB, Ethernet, display, VPU and NPU nodes; production needs the vendor BSP
Inside the RK3562
Drawn by Groundplane from the datasheet rev 1.2. Not Rockchip artwork.
- 32-bit DDR3/DDR4
- LPDDR3/LPDDR4/LPDDR4X
- eMMC 5.1
- SD 3.0
- FSPI flash
- 4x Cortex-A53 up to 2.0 GHz
- 512 KB L2
- NEON, FPU, Crypto Ext
- Mali-G52 1-Core-2EE
- 2D raster engine (RGA)
- 1 TOPS
- INT8, INT16, FP16, BF16
- 4K30 H.265/VP9 decoder
- 1080p60 H.264 decoder
- 1080p60 H.264 encoder
- JPEG codec
- VICAP
- 13 MP ISP, HDR, 3DNR
- VOP, 4 layers
- Single output, 2048x1080@60
- Crypto, TRNG
- 8 Kbit OTP
- TrustZone
- 2x MCU
- PMU, 13 power domains
- 6 PLLs, 24 MHz OSC
- 64 KB SRAM, 32 KB ROM
- PCIe 2.1 x1 or USB 3.0
- USB 2.0 host
- GbE RGMII
- 10/100 RMII
- SDIO 3.0
- MIPI DSI 4-lane
- LVDS
- RGB, BT.1120
- 2x MIPI CSI RX, 4 lanes each
- 2x CAN
- 10x UART
- 6x I2C, 3x SPI
- 3x SAI, PDM, SPDIF
- 16x PWM, SARADC
Read from the documents
Each value names the document it was read from.
| CPU | 4x Cortex-A53, up to 2.0 GHz, 32 KB I + 32 KB D L1 per core, 512 KB L2 | Datasheet Rev 1.2, 1.2.1, Fig 1-1, Table 3-2 |
|---|---|---|
| GPU | Mali-G52 1-Core-2EE, up to 900 MHz; OpenGL ES 3.2, Vulkan 1.1, OpenCL 2.0 | Datasheet Rev 1.2, 1.2.7, Table 3-2 |
| NPU | Up to 1 TOPS; INT8, INT16, FP16, BF16, TF32 | Datasheet Rev 1.2, 1.2.2 |
| Video decode | H.265 and VP9 up to 4096x2304@30; H.264 up to 1080p60 | Datasheet Rev 1.2, 1.2.5 |
| Video encode | H.264 High Profile up to 1080p60; JPEG encode up to 8192x8192 | Datasheet Rev 1.2, 1.2.5, 1.2.6 |
| Memory | 32-bit DDR3/DDR3L/LPDDR3 (2133), DDR4/LPDDR4/LPDDR4X (2666), up to 8 GB | Datasheet Rev 1.2, 1.2.3 |
| Storage | eMMC 5.1 (HS400), SD 3.0, FSPI serial flash (1/2/4-bit) | Datasheet Rev 1.2, 1.2.3 |
| Display | One output up to 2048x1080@60: 4-lane MIPI DSI (1.2 Gbps/lane), LVDS (800x1280@60), RGB, BT.656/BT.1120 | Datasheet Rev 1.2, 1.2.9, 1.2.10 |
| Camera | 2x MIPI CSI RX, up to 4 lanes each at 2.5 Gbps/lane; ISP up to 4224x3136 (13 MP@30), up to 4 sensors | Datasheet Rev 1.2, 1.2.8 |
| PCIe | 1x PCIe 2.1 x1, Root Complex only, shared with USB 3.0 | Datasheet Rev 1.2, 1.2.12 Multi-PHY |
| USB | 1x USB 3.0 DRD (shared with PCIe), 1x USB 2.0 host | Datasheet Rev 1.2, 1.2.12 |
| Ethernet | 1x GMAC (RGMII/RMII, 10/100/1000) plus 1x MAC (RMII, 10/100) | Datasheet Rev 1.2, 1.2.12 |
| CAN | 2x CAN (ISO 11898-1:2003), up to 1 Mbps, 8-byte data frames; on both RK3562 (from Rev 2.0) and RK3562J | Datasheet Rev 2.1, 1.2.12 CAN Bus |
| Other I/O | 10x UART, 6x I2C, 3x SPI, 16x PWM, 3x SAI, 8-ch PDM, SPDIF, SDIO 3.0, 16-ch 10-bit SARADC | Datasheet Rev 1.2, 1.2.11 to 1.2.13 |
| Security | Crypto engines (AES, SHA, RSA up to 4096-bit), TRNG, 8 Kbit OTP, secure boot and secure debug | Datasheet Rev 1.2, 1.2.4 |
| Temperature | Ambient 0 to 80 C (RK3562); Tj max 125 C | Datasheet Rev 1.2, Table 3-2, 4.1 |
| Package | FCCSP478L, 13.9 x 13.9 mm, 0.5 and 0.65 mm ball pitch, MSL3 | Datasheet Rev 1.2, 1.2.13, 2.4 |
Variants
| RK3562 | Commercial part. CPU up to 2.0 GHz, GPU up to 900 MHz, NPU up to 1 GHz, 1 TOPS NPU rating, ambient 0 to 80 C. | Datasheet Rev 1.2 |
|---|---|---|
| RK3562J | Industrial part, ambient -40 to 85 C. CPU 1.2 GHz in normal mode and 1.8 GHz in overdrive, GPU 700 or 900 MHz, NPU 700 or 1000 MHz. The datasheet warns that long-term overdrive, especially hot, may shorten lifetime. The J datasheet gives no TOPS figure. Same FCCSP478L package and pin list. | Datasheet Rev 2.2 |
What to watch when you design with it
Power and PMIC
The RK809 is the common pairing: Rockchip's RK3562 EVB2 device tree in mainline Linux uses an RK809 on I2C0, as do the Boardcon MINI3562 and Neardi LCB3562 modules. The vendor kernel also carries an RK817 tablet reference (rk3562-rk817-tablet-v10.dts), the choice for battery-powered designs since the RK817 adds a charger. The SoC needs separate VDD_CPU, VDD_GPU, VDD_NPU and VDD_LOGIC rails, a PMU domain and DDRPHY_VDDQ at the voltage for your DRAM type. On the RK3562J, VDD_CPU is 0.8 to 1.0 V for 1.2 GHz normal mode and up to 1.18 V for 1.8 GHz overdrive.
Sources: Datasheet Rev 1.2, Datasheet Rev 2.0, PMIC Rev 2.7, PMIC Rev 2.1, github.com, github.com, Other
DDR
One 32-bit controller supports DDR3, DDR3L, LPDDR3, DDR4, LPDDR4 and LPDDR4X, one type per board, up to 8 GB. Rockchip's EVB2 uses DDR4 and EVB1 uses LPDDR4X (per the vendor device tree names); most SoMs use LPDDR4 or LPDDR4X. DRAM training is a closed binary in rkbin (rk3562_ddr_*.bin, several frequency builds), which your boot chain has to include. No public RK3562 hardware design guide with routing rules was found; get it from Rockchip or your SoM vendor.
Sources: Datasheet Rev 1.2, github.com, github.com
High-speed interfaces
PCIe 2.1 x1 (Root Complex only) and USB 3.0 share one Multi-PHY, so pick one at design time. The mainline EVB2 device tree notes that with PCIe in use, the USB 3.0 port runs USB 2.0 only. MIPI DSI and LVDS share the same balls. There is only one video output, up to 2048x1080@60. HDMI needs an external bridge: Rockchip's vendor tree has EVB variants with an SiI9022 bridge from RGB or BT.1120.
Sources: Datasheet Rev 1.2, lists.infradead.org, github.com
Boot and maskrom
The BootROM boots from FSPI flash, eMMC or SD, and accepts firmware over the USB OTG port in device mode. Forlinx lists the boot order as FSPI, eMMC, TF card, USB. Grounding SARADC0_BOOT at power-up forces maskrom. On the OK3562J-C carrier you hold K5 and connect the USB Type-C port; Firefly boards have a Maskrom button. Bring SARADC0 and the OTG port to a header or button on your own board.
Sources: Datasheet Rev 1.2, Other V1.3, wiki.t-firefly.com
Thermal
Rockchip gives junction-to-ambient 22.6 C/W, junction-to-board 15.9 C/W and junction-to-case 3.3 C/W on a 4-layer 114.3 x 101.6 mm test board, with Tj max 125 C. The commercial part is rated for 0 to 80 C ambient, the J part for -40 to 85 C. Forlinx specifies a 38 x 38 x 10 mm thermal pad between SoM and heat sink on its carrier.
Sources: Datasheet Rev 1.2, Datasheet Rev 2.0, Other V1.3
Gotchas
Forlinx powers its SoM before the carrier (the SoM VCC_3V3_SD enables the carrier regulator) to avoid latch-up through I/O. It also warns against extra capacitance on RESETn and against doubling the SD pull-ups already on the SoM. RK3562J overdrive is a lifetime trade-off: Rockchip recommends DVFS and good heat sinking, not running at 1.8 GHz continuously.
Sources: Other V1.3, Datasheet Rev 2.0
Layout guides for the RK3562's interfaces
Public layout guidance for each interface this chip has, from vendors who publish it, plus our calculators.
LPDDR4
Point-to-point routing; TI notes that on-die termination on both ends means no board termination is needed. Byte lanes length-matched to their strobe and command/address matched to the clock, all over a solid reference plane. Impedance targets differ by vendor: TI AM62x and ADI EE-480 use 40 ohm single-ended and 80 ohm differential, Synaptics SL1680 uses 50 and 85 ohm, AMD Versal 45 and 82 ohm. Use the SoC vendor's own target and simulate.
- AM62x, AM62Lx DDR Board Design and Layout GuidelinesTexas Instruments, SPRAD06, C, 2025
- AM62Ax, AM62Px, AM62Dx LPDDR4 Board Design and Layout GuidelinesTexas Instruments, SPRAD66, B, 2024
- ADSP-2184x/ADSP-SC84x LPDDR4 Board Design GuidelinesAnalog Devices, EE-480, 1, 2026
- SL1680 General PCB Design and LPDDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001390-01, E
- DDR length matching calculatorGroundplane calculator
LPDDR4X
Same topology and matching discipline as LPDDR4, with a lower I/O voltage, so routing rules are usually published for both together. Synaptics SL1680 gives 50 ohm single-ended and 85 ohm differential for LPDDR4 and LPDDR4X; AMD Versal gives 45 and 82 ohm. Check the SoC vendor target before fixing the stackup.
- SL1680 General PCB Design and LPDDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001390-01, E
- SL1640 General PCB Design and DDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001529-01, D
- Versal Adaptive SoC PCB Design User Guide: PCB Routing Guidelines for LPDDR4/4x InterfacesAMD, UG863, 1.12, 2026
- DDR length matching calculatorGroundplane calculator
DDR4
DDR4 uses pseudo open-drain data signaling and needs a VPP supply, with command/address routed fly-by or as a balanced tree depending on device count. TI AM62x uses 40 ohm single-ended and 80 ohm differential; AMD Versal uses 50 and 90 ohm, relaxed under the BGA. Match data to strobe per byte and command/address to clock.
- AM62x, AM62Lx DDR Board Design and Layout GuidelinesTexas Instruments, SPRAD06, C, 2025
- Versal Adaptive SoC PCB Design User Guide: PCB Routing Guidelines for DDR4 InterfacesAMD, UG863, 1.12, 2026
- SL1640 General PCB Design and DDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001529-01, D
- PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex 5 FPGAs and SoCsAltera, 821801, 2026
- DDR length matching calculatorGroundplane calculator
- Via current calculatorGroundplane calculator
DDR3 / DDR3L
Fly-by command/address with termination at the end of the chain, point-to-point data lanes matched to their strobe, and a clean VREF. ST recommends 55 ohm single-ended and 100 ohm differential for DDR3 and DDR3L on STM32MP1 boards, and shows that a 4-layer board is possible with strict layer allocation.
- STM32MP1 Series DDR memory routing guidelinesSTMicroelectronics, AN5122, 3, 2019
- DDR3 Design Requirements for KeyStone DevicesTexas Instruments, SPRABI1, D, 2022
- SL2610 General PCB Design and DDR3L/DDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001629-01, A, 2025
- DDR length matching calculatorGroundplane calculator
LPDDR3
Point-to-point and normally unterminated, with command/address matched to the clock and each byte matched to its strobe. ST gives the same targets for LPDDR3 as for DDR3: 55 ohm single-ended and 100 ohm differential. Few current public guides cover LPDDR3, so treat the SoC vendor's reference layout as the stronger source.
- STM32MP1 Series DDR memory routing guidelinesSTMicroelectronics, AN5122, 3, 2019
- DDR length matching calculatorGroundplane calculator
eMMC
A single-ended bus: CLK, CMD, DAT0 to DAT7 and, for HS400, the data strobe. TI and Synaptics both route it at 50 ohm single-ended, match the group, and keep stubs short; Synaptics places a 22 or 33 ohm series resistor on CLK and STRB. At HS400 TI also checks the eMMC I/O supply impedance, not just the traces.
- AM62Px eMMC HS400 Board Design and Simulation GuidelinesTexas Instruments, SPRADP5, A, 2026
- Astra Machina Foundation Series eMMC ConfigurationSynaptics, PN 506-001594-01, D
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
SD card / SDIO
Single-ended CLK, CMD and four data lines over a solid ground plane, at constant trace width and matched length. NXP asks for clock-to-neighbor spacing greater than twice the trace height above the plane and 1.5 times for data and CMD, with 45 degree bends. UHS modes switch the I/O to 1.8 V, so a level translator often sits next to the socket.
- NVT4557/NVT4558/NVT4858 voltage-level translator layout guidelineNXP, AN13158, 1.1, 2022
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
- SD Physical Layer Simplified SpecificationSD Association, 9.10, 2023
PCIe
AC-coupled differential lanes routed with no stubs, minimal vias and back-drilled or blind vias where speed demands, with lane-to-lane skew handled by the receiver. Targets differ by guide: TI Jacinto 7 uses 85 ohm differential for lanes and 100 ohm for the reference clock, while TI's earlier SoC guide tabulates 100 ohm and, for some devices, 95 ohm. Match the target to your connector and stackup.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
USB 3.x
SuperSpeed TX and RX pairs are routed at 90 ohm differential in all three TI guides (SPRAAR7 lists 95 ohm for some devices), with AC coupling capacitors on TX, symmetric pad and via placement, and matched via counts within each pair. Keep the pairs away from the USB 2.0 pair and other aggressors, and place ESD at the connector.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
USB 2.0
One D+/D- pair at 90 ohm differential, routed in parallel for its whole length with minimal deviations at the connector and package. NXP keeps clocks and periodic signals at least 50 mils away and other signals at least 20 mils away from the pair.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
MIPI DSI
MIPI D-PHY clock and data lanes are routed as 100 ohm differential pairs over a solid reference; TI Jacinto 7 allows no stubs, 2 vias per trace and 40 ps lane-to-lane skew. Connectors and flex cables to the panel are usually the largest discontinuity, so keep the board segment short and clean.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex 5 FPGAs and SoCsAltera, 821801, 2026
MIPI CSI-2
Same D-PHY rules as DSI: 100 ohm differential lanes in both TI guides, with lane-to-lane skew bounded (40 ps in TI Jacinto 7). Size the lane count and lane rate from the sensor's output format before routing.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex 5 FPGAs and SoCsAltera, 821801, 2026
- MIPI CSI-2 bandwidth calculatorGroundplane calculator
LVDS
Tightly coupled differential pairs terminated at the receiver in 100 ohm, with TI's EMI guide asking for 100 ohm differential traces within 5 percent. Keep pairs matched and away from other aggressors, and avoid stubs and reference plane gaps along the route to the panel connector.
- LVDS Owner's Manual: Including High-Speed CML and Signal ConditioningTexas Instruments, SNLA187, 4th edition, 2008
- High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes DesignsTexas Instruments, SNLA302, 2018
- LVDS SerDes Gen I PCB and Interconnect Design-In GuidelinesTexas Instruments, SNLA008, A, 2018
Ethernet (RGMII / RMII)
TI routes MAC-to-PHY (MII family) traces at 50 ohm single-ended, under 6 inches, matched within 20 mils for gigabit, and the PHY-side MDI pairs at 100 ohm differential. RGMII also needs a 1.5 to 2.0 ns clock-to-data delay, added on the board or inside the MAC or PHY (RGMII-ID); decide which before layout so it is not applied twice.
- Ethernet PHY PCB Design Layout ChecklistTexas Instruments, SNLA387, 2021
- PCB Design Guideline for RGMII InterfaceRenesas, R01AN6272EJ0141, 1.41, 2026
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
Board-level design guides
Impedance and timing, power, thermal and ESD guidance that applies to any board around this chip.
Impedance and timing
Every high-speed interface on the board comes down to the same two numbers: the trace impedance your stackup actually gives, and the delay each trace adds. Set the stackup with your fab first, then route to its impedance table and match lengths in time, not millimeters, where the layers differ.
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- PCB impedance calculatorGroundplane calculator
- PCB propagation delay calculatorGroundplane calculator
Power delivery
For each switching regulator, place and route the input capacitor first, keep the switching current loop small, and keep the switch node short. Give the SoC rails solid planes and decoupling at the balls, and size current-carrying copper and vias for the real load.
- Five steps to a great PCB layout for a step-down converterTexas Instruments, SLYT614, 2015
- AN-1149 Layout Guidelines for Switching Power SuppliesTexas Instruments, SNVA021, C, 2013
- AN-1229 SIMPLE SWITCHER PCB Layout GuidelinesTexas Instruments, SNVA054, C, 2013
- Buck converter calculatorGroundplane calculator
- LDO power dissipation calculatorGroundplane calculator
- PCB trace width calculatorGroundplane calculator
- Via current calculatorGroundplane calculator
Thermal
Theta-JA is measured on a JEDEC test board that carries most of the heat, so it does not transfer directly to a product board; use it to compare packages and use the psi metrics for estimates. Thermal vias under the package, copper area and copper thickness move the most heat into the board.
- Semiconductor and IC Package Thermal MetricsTexas Instruments, SPRA953, D, 2024
- AN-2020 Thermal Design By Insight, Not HindsightTexas Instruments, SNVA419, C, 2013
- Heatsink thermal resistance calculatorGroundplane calculator
- LDO power dissipation calculatorGroundplane calculator
ESD protection
Place the TVS as close to the connector as design rules allow, route from the connector to the TVS with no stub, and keep the protected IC further from the TVS than the TVS is from the connector. Choose parts by clamping performance and by capacitance low enough for the interface speed.
- ESD Protection Layout GuideTexas Instruments, SLVA680, A, 2022
- Reading and Understanding an ESD Protection Data SheetTexas Instruments, SLLA305, A
- TPD12S016 PCB Layout Guidelines for HDMI ESDTexas Instruments, SLLA324, 2012
- PCB conductor spacing calculator (IPC-2221)Groundplane calculator
Rockchip's hardware design guide
Rockchip's hardware design guide, EVB reference schematics and DDR templates come from Rockchip or an authorized agent, usually under NDA, or through your SoM vendor. We do not link copies circulating elsewhere. The vendor schematics and open designs on the Boards tab are real, shipped layouts on the RK3562 and the best public reference.
BSP, mainline and toolkits
| Area | Status | Links |
|---|---|---|
| Vendor BSP kernel | Rockchip's kernel branches develop-5.10, develop-6.1, develop-6.6 and develop-6.12 all carry rk3562.dtsi, plus EVB, tablet and RK3562J device trees. Board vendors ship Linux 5.10.198 and 6.1.118 (Forlinx) and 6.1.99 (MYIR, Boardcon).Checked 2026-10-13 | |
| Mainline Linux | The SoC dtsi and the Rockchip EVB2 board landed in Linux 6.16. As of 7.3-rc7 the mainline dtsi covers the CPUs (OPPs to 2016 MHz), PCIe 2.1, eMMC, SD/SDIO, FSPI, UART, I2C, SPI, PWM, SARADC and OTP. It also has a Mali-G52 GPU node (Panfrost binding), disabled in the dtsi and not enabled on the EVB2. There are no USB, Ethernet, display, VPU or NPU nodes yet.Checked 2026-10-13 | |
| U-Boot | Rockchip's vendor U-Boot (next-dev) supports RK3562, and SoM vendors ship U-Boot 2017.09. Mainline U-Boot only carries the synced upstream device trees, with no RK3562 SoC support in arch/arm/mach-rockchip. Barebox merged RK3562 EVB2 and KickPi K3 board support in February 2026. Boot firmware (BL31, DDR init, SPL, usbplug) is binary-only in rkbin; mainline TF-A has no RK3562 platform.Checked 2026-10-13 | |
| NPU toolkit | RKNN-Toolkit2 has supported RK3562 since v1.5.0; the changelog runs to v2.5.0, which adds RK3562 mini-runtime and MatMul w4a8/w4a16. RKLLM lists the RK3562 series as a supported platform. The mainline Rocket NPU driver does not cover RK3562.Checked 2026-10-13 | |
| Video (MPP) | Rockchip MPP lists RK3562 as a supported chip. The decoder and encoder have no mainline (V4L2) support yet.Checked 2026-10-13 | |
| 2D (RGA) | librga lists RK3562 among supported chips.Checked 2026-10-13 | |
| Android | Board vendors ship Android 13 (Graperain G3562) and Android 14 (Forlinx OK3562J-C, Boardcon EM3562).Checked 2026-10-13 | |
| Distributions | Armbian added a KickPi K3B board config in September 2026: an edge kernel with out-of-tree RK3562 patches (USB, GMAC, VOP2, MIPI DSI, SAI) and patched mainline U-Boot v2026.07. Vendors ship Debian 12, Ubuntu 22.04 and Buildroot images on their vendor kernels.Checked 2026-10-13 | |
| Community | The chip is common in low-cost tablets and dictionary pens. rk3562deb boots Debian 13 from SD on the Doogee U10 tablet (RK3562, RK817 PMIC), with display, Wi-Fi, audio and the NPU working and cameras partly working, on a vendor-derived 6.1 kernel.Checked 2026-10-13 |
RK3562 on GitHub
Repositories for this chip: vendor code, mainline work, toolkits, distributions and open hardware.
- Vendor BSPJeffyCN/meta-rockchipYocto BSP layer maintained by a Rockchip engineer, with RK3562 machine configs. Last commit 2026-10.
- Kernelrockchip-linux/kernelRockchip BSP kernel; RK3562 is supported on develop-5.10 and develop-6.1 with around 50 device trees. Last commit 2026-08.
- Kerneltorvalds/linuxMainline Linux has rk3562.dtsi with only the EVB2 board so far. Last commit 2026-10.
- Bootloaderrockchip-linux/u-bootRockchip U-Boot; next-dev has arch/arm/mach-rockchip/rk3562. Mainline U-Boot has no RK3562 support. Last commit 2026-08.
- Bootloaderrockchip-linux/rkbinDDR init, loaders and BL31; bin/rk35 holds the rk3562 binaries required to boot. Last commit 2026-08.
- NPUairockchip/rknn-toolkit2RKNN-Toolkit2 converter and RKNPU2 runtime with RK3562 listed as a supported platform. Last commit 2026-10.
- NPUairockchip/rknn-llmRKLLM runtime; RK3562 is one of the four supported platforms for on device LLM inference. Last commit 2026-09.
- NPUairockchip/rknn_model_zooReference model conversions and demos with RK3562 listed for every vision model. Last commit 2026-10.
- Mediarockchip-linux/mppMedia Process Platform; RK3562 is listed in the README for hardware decode and encode. Last commit 2026-09.
- Mediaairockchip/librgaRGA 2D acceleration library with RK3562 in its supported chip list. Last commit 2026-06.
- Distributionarmbian/buildArmbian build framework; the KickPi K3B is the one RK3562 board config. Last commit 2026-10.
- Toolsrockchip-linux/rkdeveloptoolRockchip open source USB flashing tool for maskrom and loader mode, the Linux and macOS alternative to RKDevTool. Last commit 2025-03.
- Toolsxboot/xrockLow level maskrom and loader mode tool that can also init DDR and run code over USB; chip support is listed in its README. Last commit 2026-08.
- Communityblakeblackshear/frigateFrigate NVR RKNN detector lists rk3562 as a supported SoC. Last commit 2026-10.
- Communitytech4bot/rk3562debDebian 13 brought up on the RK3562 Doogee U10 tablet without a BSP, a useful log of what the chip needs to boot. Last commit 2026-06.
RK3562 system on modules
Any of these can sit on a carrier board we design.
| Module | Vendor | Connector | RAM | Design files | Price | Buy |
|---|---|---|---|---|---|---|
| FET3562J-C | Forlinx | 3x 80-pin board-to-board, 0.5 mm pitch | 1 or 2 GB LPDDR4 | Product brief public; carrier schematic and PCB provided after purchase | ||
| iCore-3562Q / iCore-3562JQ | Firefly | 3x 80-pin BTB, 0.5 mm pitch | 1 to 4 GB LPDDR4 in store (spec lists up to 8 GB) | Specification PDF only | USD 129 (iCore-3562Q 2 GB/8 GB, Firefly store) | |
| MYC-YR3562 | MYIR | 164-pin castellated plus 58-pin LGA (solder-down) | 1 or 2 GB LPDDR4 | Overview PDF and 3D STEP public; schematics via developer center | USD 71 (RK3562J 1 GB/8 GB sample, MYIR) | |
| MINI3562 | Boardcon | 2x 100-pin board-to-board, 0.4 mm pitch | 2 to 8 GB LPDDR4X | Hardware manual PDF with reference carrier circuits, connector pinout, 3D model | ||
| G3562 SoM | Graperain | 260-pin gold finger, 1 mm pitch | 2 GB LPDDR4 standard, 4 or 8 GB custom | Hardware manual public; schematic PDF supplied with purchase | ||
| ECK40-E2E32-I | Ebyte | Castellated holes plus LGA pads | 2 GB | USD 256.50 (Ebyte on Tindie) | ||
| LCB3562 | Neardi | 3x 80-pin B2B | 1 to 4 GB LPDDR4/LPDDR4X | Product manual PDF (Chinese) |
Every public RK3562 board
| Board | Vendor | Type | RAM | Notable I/O | Design files | Price | Buy |
|---|---|---|---|---|---|---|---|
| OK3562J-C | Forlinx | Dev kit, FET3562J-C on a 130 x 190 mm carrier | 1 or 2 GB LPDDR4 | GbE plus 10/100, 2x isolated CAN, 3x MIPI CSI (4+2+2), MIPI DSI, LVDS, mini PCIe 4G | Online hardware manual; carrier schematic and PCB provided after purchase | ||
| AIO-3562JQ | Firefly | SBC, iCore-3562JQ on an industrial carrier, 9 to 36 V input | 1 or 2 GB | Isolated RS485, RS232, CAN, Opto-isolated DIN, relay DOUT, GbE plus 10/100, USB 3.0 OTG | Specification PDF only | USD 219 (1 GB/8 GB, Firefly store) | |
| MYD-YR3562 | MYIR | Dev kit, MYC-YR3562 on a 90 x 120 mm, 6-layer carrier | 2 GB LPDDR4 | M.2 NVMe PCIe slot, HDMI (LT8912B bridge), MIPI DSI, 3x MIPI CSI, Wi-Fi, Bluetooth | Overview and quick start PDFs public; schematics via developer center | USD 135 (RK3562 2 GB/16 GB, MYIR) | |
| EM3562 | Boardcon | SBC, MINI3562 on a 160 x 115 mm base board | 2 to 8 GB | 8x AHD camera inputs, GbE, M.2 NVMe, mPCIe 4G | Linux user manual only | ||
| G3562 Development Board | Graperain | Dev kit, G3562 SoM on a 120 x 90 mm carrier | 2 GB LPDDR4 | GbE plus 10/100, MIPI DSI, LVDS, 2x MIPI CSI, M.2, 4G | Hardware manual public; schematic PDF supplied with purchase | ||
| M3562 | Pretech | SBC, 83.8 x 84 mm, 4-layer | 2 GB LPDDR4 | MIPI DSI, eDP, GbE, Wi-Fi 6, Bluetooth 5.2, USB 3.0 Type-A | None listed |
Prices and links as checked on the dates in our data; the latest check on this page was 2026-10-13.
Buying the chip
Both grades are sold in single quantities through LCSC. We could not confirm Rockchip's authorized distributor list for this part. Volume pricing and lead time are not public. SoM vendors (Forlinx, MYIR, Firefly, Boardcon) are the practical route if you do not want to do the DDR layout.
- LCSC (RK3562, C29779896)
- USD 11.91 at 1 pc, 8.07 at 119+; 80 in stock; tray of 119; MOQ 1
- LCSC (RK3562J, C42404520)
- USD 14.60 at 1 pc, 11.61 at 119+; 149 in stock; tray of 119; MOQ 1
- JLCPCB parts library
- Both RK3562 and RK3562J are listed for PCBA assembly
Datasheet, TRM and design documents
Linked where they are publicly hosted; we do not rehost Rockchip documents. These are third-party documents: we are not responsible for their accuracy, availability or confidentiality status. Disclosure.
- DatasheetRK3562 DatasheetRev 1.2 · 2024-04-28 · hosted by LCSC · checked 2026-10-13
- DatasheetRK3562J DatasheetRev 2.0 · 2024-11-04 · hosted by LCSC · checked 2026-10-13
- OtherOK3562J-C User Hardware Manual (SoM connector, power, boot, carrier notes)V1.3 · hosted by Forlinx · checked 2026-10-13
- OtherMINI3562 Reference User Manual (includes hardware design guide chapter)2024-12-02 · hosted by Boardcon · checked 2026-10-13
- Product briefiCore-3562Q / iCore-3562JQ SpecificationV1.0 · 2024-11-21 · hosted by Firefly · checked 2026-10-13
- Product briefMYC-YR3562 System-On-Module Overviewhosted by MYIR · checked 2026-10-13
- DatasheetRK3562 DatasheetRev 2.1 · 2025-09-24 · community mirror (rockchip.fr), not hosted by Rockchip · checked 2026-10-13
- DatasheetRK3562 DatasheetRev 2.0 · 2024-11-04 · community mirror (rockchip.fr), not hosted by Rockchip · checked 2026-10-13
- DatasheetRK3562J DatasheetRev 2.2 · 2025-09-30 · community mirror (rockchip.fr), not hosted by Rockchip · checked 2026-10-13
- TRMRockchip RK3562 TRM Part 1Rev 1.0 · 2023-08-03 · community mirror (rockchip.fr), not hosted by Rockchip · checked 2026-10-13
- TRMRockchip RK3562 TRM Part 2Rev 1.0 · 2023-08-03 · community mirror (rockchip.fr), not hosted by Rockchip · checked 2026-10-13
- PMICRockchip RK809 DatasheetRev 2.7 · 2026-01-13 · community mirror (rockchip.fr), not hosted by Rockchip · checked 2026-10-13
- PMICRockchip RK817 DatasheetRev 2.1 · 2023-03-20 · community mirror (rockchip.fr), not hosted by Rockchip · checked 2026-10-13
Questions about the RK3562
Not the RK3562 itself. We have designed and brought up boards on the Rockchip RV1106, RV1126, RV1126B, RK3566, RK3568, RK3576 and RK3588, and on the Allwinner T507 and A527/T527. The work carries over: power tree, DDR and high-speed layout, bring-up and the BSP, read against this chip's own datasheet.
Rockchip does not host them on its own sites. The distributor LCSC hosts the RK3562 Datasheet Rev 1.2 (2024-04-28) and the RK3562J Datasheet Rev 2.0 (2024-11-04), linked under Documents. Newer revisions (RK3562 Rev 2.1, RK3562J Rev 2.2), the TRM (Part 1 and Part 2, Rev 1.0, 2023-08-03) and the RK809 and RK817 PMIC datasheets are only on the community mirror rockchip.fr; they are linked and labeled as mirror copies. No public hardware design guide was found; ask Rockchip or your SoM vendor.
Same die and package with different ratings. The RK3562 runs up to 2.0 GHz at 0 to 80 C ambient. The RK3562J is rated -40 to 85 C and runs 1.2 GHz in normal mode or 1.8 GHz in overdrive, which Rockchip says can shorten lifetime if run continuously, especially hot. LCSC lists the J part about USD 2.70 to 3.50 higher per chip.
No. The display outputs are MIPI DSI (4 lanes), LVDS, parallel RGB and BT.656/BT.1120, with one output up to 2048x1080@60. Rockchip's vendor kernel has EVB device trees that drive an SiI9022 bridge from RGB or BT.1120 for HDMI.
The datasheet rates it at up to 1 TOPS with INT8, INT16, FP16, BF16 and TF32 support. RKNN-Toolkit2 has supported it since v1.5.0, and RKLLM lists the RK3562 series as supported. The RK3562J datasheet gives no TOPS figure, and its NPU clock is 700 MHz in normal mode.
Partly. The SoC and Rockchip's EVB2 board have been in mainline since Linux 6.16. As of 7.3-rc7 that covers boot, storage, PCIe and low-speed peripherals, but USB, Ethernet, display, video and NPU are not upstream. Armbian carries out-of-tree patches for USB, GMAC and display on the KickPi K3B. Products today run Rockchip's 5.10 or 6.1 BSP kernels.
Verified on vendor pages: Forlinx FET3562J-C (3x 80-pin B2B), Firefly iCore-3562Q/JQ (3x 80-pin BTB, from USD 129), MYIR MYC-YR3562 (castellated plus LGA, from USD 71 sample), Boardcon MINI3562 (2x 100-pin B2B), Graperain G3562 (260-pin gold finger), Ebyte ECK40 (castellated plus LGA) and Neardi LCB3562 (3x 80-pin B2B). None publish full layout sources.
Related chips and reading
- RK3566HMI, e-ink readers, handhelds, CM4-class SoMs, small routers
- RK3568Routers, NAS, gateways, NVR, industrial HMI
- RK3576Edge AI boxes, HMI, NVR, Arm PC, tablets
- RK3528TV boxes, media players, small routers
- RK3326 / PX30Handhelds, HMI panels, smart audio, kiosks
- RV1126BAI IP cameras, multi-camera vision
We'll design your RK3562 board.
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Links and facts on this page checked 2026-10-13. Spotted something out of date? Tell us through the contact form.
Compiled from publicly available sources: datasheets, technical reference manuals, vendor product pages, schematics and source code published by their owners and third parties. We link to documents where others host them and do not host, endorse or vouch for them. Everything on these pages, including our own specs, summaries, block diagrams, comparisons, calculators and design notes, is for reference only and may contain errors or be out of date. It is provided as is, and Groundplane is not responsible for errors in it, for third-party documents, or for any design, board or decision based on it. Always check the manufacturer's current datasheet, reference manual and design guidance before you design a board. Rockchip, Allwinner, Raspberry Pi and other product names are trademarks of their owners; we are not affiliated with any of them. See our disclosure.