RK3528
Low-cost quad Cortex-A53 media SoC for 4K60 HEVC playback, set-top boxes and small routers: one HDMI 2.0b output, one shared PCIe 2.1 x1 or USB 3.0 lane, no NPU, no camera input.
- CPU
- 4x Cortex-A53
- GPU
- Mali-450
- NPU
- None
- Video
- 4K60 H.265/H.264/AVS2 decode, 1080p60 encode
- PCIe
- 1x Gen2 x1 (shared with USB 3.0)
What the RK3528 is for
Right for
- 4K60 HEVC, H.264 and AVS2 playback boxes with HDMI 2.0b and HDR10/HLG output
- Dual-Ethernet travel routers and gateways (1 GbE RGMII MAC plus a PCIe NIC or the on-chip 10/100 PHY)
- Cost-driven Linux appliances that need 1 to 4 GB of LPDDR4 and eMMC, nothing more
- DVB or IPTV receivers: two TS inputs with CSA2 descrambling and an ISO-7816 smart card interface
- Retrofits of RK3328-class designs that need a newer, still-shipping part
Wrong for
- Anything needing an NPU: the datasheet lists none
- Cameras or vision: no MIPI CSI and no ISP in the datasheet
- Designs needing both PCIe and USB 3.0: they share one combo PHY
- VP9 or AV1 streaming boxes that need hardware decode: neither codec is in the datasheet decoder list
- MIPI DSI, LVDS or eDP panels, or more than one digital display: the only digital output is HDMI
Cost and constraints
- The single PCIe 2.1 x1 / USB 3.0 combo lane is the whole high-speed budget; a second NIC or NVMe uses it up
- Memory is one 32-bit channel with 4 GB addressing
- No companion PMIC on public boards: CPU and logic rails are PWM-controlled discrete bucks, which keeps BOM cost low
- Mainline Linux had no display (VOP/HDMI) or video decoder support as of 7.3-rc7; media products run the vendor 6.1 BSP
- No TRM or hardware design guide is publicly hosted; layout knowledge comes from vendor schematics
Inside the RK3528
Drawn by Groundplane from the datasheet v1.2. Not Rockchip artwork.
- 32-bit DDR3/DDR4
- LPDDR3/LPDDR4/LPDDR4X
- eMMC 5.1 HS400
- SD 3.0
- FSPI NOR/NAND
- 4x Cortex-A53, NEON/FPU
- 32 KB L1 I/D per core
- Shared L2 cache
- Mali-450
- OpenGL ES 2.0, OpenVG 1.1
- 4K60 H.265/H.264/AVS2 decoder
- 1080p60 H.265/H.264 encoder
- JPEG decode and encode
- 2D graphics engine
- VDPP deinterlace and scaler
- VOP, 2 video ports
- HDR10, HLG, HDR Vivid
- Crypto engine, TRNG
- Firewall
- OTP 8 Kbit
- Cortex-M0 MCU
- 5 PLLs, 24 MHz osc
- Timers, watchdogs, 3x DMAC
- BootROM, 64 KB system SRAM
- PCIe 2.1 x1 or USB 3.0
- USB 2.0 OTG
- USB 2.0 host
- 1 GbE MAC (RGMII)
- 10/100 MAC + PHY
- HDMI 2.0b TX
- CVBS out
- Line-out DAC
- SAI, PDM, SPDIF
- 8x UART, 8x I2C, 2x SPI
- 8x PWM, 4x SARADC
- SDIO 3.0
- 2x TS in, smart card
Read from the documents
Each value names the document it was read from.
| CPU | 4x Arm Cortex-A53 (Armv8-A), 32 KB L1 I/D per core, shared L2, NEON/FPU, TrustZone; Cortex-M0 MCU in the PMU domain | Datasheet V1.2, 1.2.1, 1.2.4, Fig.1-1 |
|---|---|---|
| CPU clock | Not stated in the datasheet; the mainline device tree tops out at a 2016 MHz OPP | Other v7.3-rc7 |
| GPU | Arm Mali-450, OpenGL ES 1.1/2.0, OpenVG 1.1 | Datasheet V1.2, 1.2.2 |
| NPU | None listed | Datasheet V1.2 |
| Video decode | H.265 Main/Main10 and H.264 up to 4Kx2K@60; AVS2 4Kx2K@60; MPEG-1/2/4, VC-1, AVS, AVS+ up to 1080p60; H.263 576p60; JPEG up to 8176x8176 | Datasheet V1.2, 1.2.5, 1.2.6 |
| Video encode | H.264 HP@L4.2 and H.265 Main@L4.1 up to 1920x1080@60; JPEG encode | Datasheet V1.2, 1.2.5 |
| Memory | 32-bit DDR3/DDR3L/LPDDR3-2133, DDR4-2400, LPDDR4/LPDDR4X-2400; 4 GB addressing space | Datasheet V1.2, 1.2.3 |
| Display | HDMI 2.0b TX, 4096x2304@60 on video port 0, HDCP 1.4/2.2, CEC; CVBS PAL/NTSC 720x576 on video port 1 via a 10-bit VDAC; HDR10, HLG, HDR Vivid | Datasheet V1.2, 1.2.9, 1.2.10 |
| Camera | No MIPI CSI or ISP listed | Datasheet V1.2 |
| PCIe | 1x PCIe 2.1 x1, Root Complex only, 5 GT/s; PHY shared with USB 3.0 | Datasheet V1.2, 1.2.12 |
| USB | 1x USB 3.0 (5 Gbps) DRD on the PCIe combo PHY; 1x USB 2.0 OTG; 1x USB 2.0 host. Either PCIe plus USB 2.0 OTG, or USB 3.0 | Datasheet V1.2, 1.2.12, notes |
| Ethernet | 1x 10/100/1000 MAC (RGMII, RMII); 1x 10/100 MAC with integrated PHY | Datasheet V1.2, 1.2.12 |
| Storage | eMMC 5.1 HS400 with CMDQ; SD 3.0; SDIO 3.0; FSPI serial NOR/NAND (1, 2 or 4 bit) | Datasheet V1.2, 1.2.3, 1.2.12 |
| Audio | 2x 8-channel and 2x 2-channel SAI (one each wired to HDMI and the internal codec), 8-channel PDM in, SPDIF, 24-bit stereo line-out DAC | Datasheet V1.2, 1.2.11 |
| Other I/O | 8x UART, 8x I2C, 2x SPI, 8x PWM, 4-channel 10-bit SARADC, 2x TS input with CSA2 descrambling, ISO-7816 smart card, 8 Kbit OTP | Datasheet V1.2, 1.2.12, 1.2.13 |
| Security | Crypto engine (AES, SM4, DES/TDES, SHA-1/256, MD5, SM3, HMAC, RSA up to 4096-bit PKA, SM2/SM3/SM4 cipher), TRNG, secure OTP, firewall | Datasheet V1.2, 1.2.4 |
| Core supplies | CPU, GPU and LOGIC 0.81 V min, 0.90 V typ; GPIO banks 1.8 V or 3.3 V | Datasheet V1.2, Table 3-2 |
| Thermal | Junction below 125 C; theta-JA 22.8, theta-JB 9.3, theta-JC 6.87 (4-layer 114.3 x 101.6 mm test board) | Datasheet V1.2, Chapter 4 |
| Package | WBBGA401L, 13.3 x 13.5 mm body, 0.3 mm balls, 0.65/0.6 mm pitch, MSL3, SnAgCu | Datasheet V1.2, 1.2.13, 2.4, 2.5 |
Variants
| RK3528A | The variant on every public board found. Supports DDR3/DDR3L/LPDDR3-2133 as well as DDR4 and LPDDR4/4X-2400 (unchanged in Rev 1.4); this page is written from its V1.2 datasheet. Rev 1.4 drops the separate SM2/SM3/SM4 cipher line that V1.2 lists, keeping SM3 hashing and SM4 modes. RK3528A-D is the same part with the Dolby Audio function. | Datasheet V1.4 |
|---|---|---|
| RK3528 | Original part number (datasheet V1.0, 2023-05-10). Same package, CPU, GPU, video and I/O list as the RK3528A, but Rev 1.4 lists only DDR4/LPDDR4/LPDDR4X (no DDR3 or LPDDR3) and keeps the SM2/SM3/SM4 cipher line that RK3528A Rev 1.4 drops. RK3528-D adds the Dolby function. Mainline Linux uses the rockchip,rk3528 compatible for both. | Datasheet V1.4 |
What to watch when you design with it
Power and PMIC
Public RK3528 boards use no PMIC. The ROCK 2A schematic block diagram labels the supply as discrete buck and LDO, and the mainline device trees for ROCK 2A/2F, E20C and NanoPi Zero2 drive vdd_arm (0.746 to 1.201 V) and vdd_logic (0.705 to 1.006 V) as PWM regulators on PWM1 and PWM2. On the ROCK 2 boards the Mali GPU is supplied from vdd_logic rather than a separate GPU rail. The datasheet gives CPU, GPU and LOGIC 0.90 V typical, 0.81 V minimum, plus 0.9 V and 1.8 V analog rails for the HDMI, USB, PCIe/USB3 and FE PHY blocks.
Sources: Datasheet V1.2, Board schematic V1.2, git.kernel.org, git.kernel.org
DDR
One 32-bit channel, one DRAM type per design, 4 GB addressing. DDR_VDDQ is 1.5 V (DDR3), 1.35 V (DDR3L), 1.2 V (DDR4, LPDDR3), 1.1 V (LPDDR4) and 0.6 V VDDQL for LPDDR4X. Rockchip publishes DDR init blobs at 1056 MHz in rkbin, including variants named for 2-layer PCBs ("2L_PCB") and 4-bit layouts, which indicates Rockchip supports 2-layer RK3528 boards. The public SBCs (ROCK 2A/2F, E20C, NanoPi Zero2, Sige1) use LPDDR4 or LPDDR4X. No public DDR routing guide was found.
Sources: Datasheet V1.2, Other, Board schematic V1.2
High-speed interfaces
PCIe 2.1 x1 and USB 3.0 share one combo PHY, so a board gets one or the other; Radxa states the ROCK 2A cannot use PCIe and USB 3.0 at the same time. A common pattern for dual-Ethernet routers is RGMII to an external PHY (RTL8211F on HINLINK H28K) plus a PCIe NIC (RTL8111H on H28K). The 10/100 MAC has an on-chip PHY, so a second, slower port needs only magnetics.
Sources: Datasheet V1.2, Board schematic, radxa.com
Boot and maskrom
The BootROM boots from FSPI, eMMC or SD and falls back to USB download. On the ROCK 2A the boot order is set by a resistor divider on SARADC_IN0_BOOT: no pull-up gives USB maskrom only, and other ratios select FSPI then USB, eMMC then USB, or eMMC then SD then USB. Maskrom uses the USB 2.0 OTG port (the Type-C device port and MASK button on the NanoPi Zero2). Rockchip ships rk3528_usbplug and rk3528_spl loaders in rkbin. Debug UART on vendor boards runs at 1500000 baud.
Sources: Datasheet V1.2, Board schematic V1.2, Other, wiki.friendlyelec.com
Thermal
The datasheet sets the junction limit below 125 C and gives theta-JA 22.8 on a 4-layer test board; maximum ambient in the operating table is 80. Radxa rates the ROCK 2A for 0 to 50 C and says the SoC throttles at 80 C, recommending a heatsink for sustained load.
Sources: Datasheet V1.2, Product brief Revision 1.1
Gotchas
The datasheet decoder list has no VP9 and no AV1, which matters for streaming boxes. The HDMI block is HDMI 2.0b in the datasheet even where board pages say HDMI 2.1. Mainline U-Boot still needs the Rockchip BL31 and DDR TPL binaries from rkbin. Mainline Linux had no VOP, HDMI or VPU nodes as of 7.3-rc7, so a media product today is a vendor 6.1 BSP product.
Sources: Datasheet V1.2, Other, Other v7.3-rc7
Layout guides for the RK3528's interfaces
Public layout guidance for each interface this chip has, from vendors who publish it, plus our calculators.
LPDDR4
Point-to-point routing; TI notes that on-die termination on both ends means no board termination is needed. Byte lanes length-matched to their strobe and command/address matched to the clock, all over a solid reference plane. Impedance targets differ by vendor: TI AM62x and ADI EE-480 use 40 ohm single-ended and 80 ohm differential, Synaptics SL1680 uses 50 and 85 ohm, AMD Versal 45 and 82 ohm. Use the SoC vendor's own target and simulate.
- AM62x, AM62Lx DDR Board Design and Layout GuidelinesTexas Instruments, SPRAD06, C, 2025
- AM62Ax, AM62Px, AM62Dx LPDDR4 Board Design and Layout GuidelinesTexas Instruments, SPRAD66, B, 2024
- ADSP-2184x/ADSP-SC84x LPDDR4 Board Design GuidelinesAnalog Devices, EE-480, 1, 2026
- SL1680 General PCB Design and LPDDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001390-01, E
- DDR length matching calculatorGroundplane calculator
LPDDR4X
Same topology and matching discipline as LPDDR4, with a lower I/O voltage, so routing rules are usually published for both together. Synaptics SL1680 gives 50 ohm single-ended and 85 ohm differential for LPDDR4 and LPDDR4X; AMD Versal gives 45 and 82 ohm. Check the SoC vendor target before fixing the stackup.
- SL1680 General PCB Design and LPDDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001390-01, E
- SL1640 General PCB Design and DDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001529-01, D
- Versal Adaptive SoC PCB Design User Guide: PCB Routing Guidelines for LPDDR4/4x InterfacesAMD, UG863, 1.12, 2026
- DDR length matching calculatorGroundplane calculator
DDR4
DDR4 uses pseudo open-drain data signaling and needs a VPP supply, with command/address routed fly-by or as a balanced tree depending on device count. TI AM62x uses 40 ohm single-ended and 80 ohm differential; AMD Versal uses 50 and 90 ohm, relaxed under the BGA. Match data to strobe per byte and command/address to clock.
- AM62x, AM62Lx DDR Board Design and Layout GuidelinesTexas Instruments, SPRAD06, C, 2025
- Versal Adaptive SoC PCB Design User Guide: PCB Routing Guidelines for DDR4 InterfacesAMD, UG863, 1.12, 2026
- SL1640 General PCB Design and DDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001529-01, D
- PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex 5 FPGAs and SoCsAltera, 821801, 2026
- DDR length matching calculatorGroundplane calculator
- Via current calculatorGroundplane calculator
DDR3 / DDR3L
Fly-by command/address with termination at the end of the chain, point-to-point data lanes matched to their strobe, and a clean VREF. ST recommends 55 ohm single-ended and 100 ohm differential for DDR3 and DDR3L on STM32MP1 boards, and shows that a 4-layer board is possible with strict layer allocation.
- STM32MP1 Series DDR memory routing guidelinesSTMicroelectronics, AN5122, 3, 2019
- DDR3 Design Requirements for KeyStone DevicesTexas Instruments, SPRABI1, D, 2022
- SL2610 General PCB Design and DDR3L/DDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001629-01, A, 2025
- DDR length matching calculatorGroundplane calculator
LPDDR3
Point-to-point and normally unterminated, with command/address matched to the clock and each byte matched to its strobe. ST gives the same targets for LPDDR3 as for DDR3: 55 ohm single-ended and 100 ohm differential. Few current public guides cover LPDDR3, so treat the SoC vendor's reference layout as the stronger source.
- STM32MP1 Series DDR memory routing guidelinesSTMicroelectronics, AN5122, 3, 2019
- DDR length matching calculatorGroundplane calculator
eMMC
A single-ended bus: CLK, CMD, DAT0 to DAT7 and, for HS400, the data strobe. TI and Synaptics both route it at 50 ohm single-ended, match the group, and keep stubs short; Synaptics places a 22 or 33 ohm series resistor on CLK and STRB. At HS400 TI also checks the eMMC I/O supply impedance, not just the traces.
- AM62Px eMMC HS400 Board Design and Simulation GuidelinesTexas Instruments, SPRADP5, A, 2026
- Astra Machina Foundation Series eMMC ConfigurationSynaptics, PN 506-001594-01, D
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
SD card / SDIO
Single-ended CLK, CMD and four data lines over a solid ground plane, at constant trace width and matched length. NXP asks for clock-to-neighbor spacing greater than twice the trace height above the plane and 1.5 times for data and CMD, with 45 degree bends. UHS modes switch the I/O to 1.8 V, so a level translator often sits next to the socket.
- NVT4557/NVT4558/NVT4858 voltage-level translator layout guidelineNXP, AN13158, 1.1, 2022
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
- SD Physical Layer Simplified SpecificationSD Association, 9.10, 2023
PCIe
AC-coupled differential lanes routed with no stubs, minimal vias and back-drilled or blind vias where speed demands, with lane-to-lane skew handled by the receiver. Targets differ by guide: TI Jacinto 7 uses 85 ohm differential for lanes and 100 ohm for the reference clock, while TI's earlier SoC guide tabulates 100 ohm and, for some devices, 95 ohm. Match the target to your connector and stackup.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
USB 3.x
SuperSpeed TX and RX pairs are routed at 90 ohm differential in all three TI guides (SPRAAR7 lists 95 ohm for some devices), with AC coupling capacitors on TX, symmetric pad and via placement, and matched via counts within each pair. Keep the pairs away from the USB 2.0 pair and other aggressors, and place ESD at the connector.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
USB 2.0
One D+/D- pair at 90 ohm differential, routed in parallel for its whole length with minimal deviations at the connector and package. NXP keeps clocks and periodic signals at least 50 mils away and other signals at least 20 mils away from the pair.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
HDMI
Four TMDS pairs (three data, one clock) at 100 ohm differential, as both TI guides state, with tight intra-pair matching and as few vias as possible between the SoC and the connector. HDMI also needs 5 V supply switching, DDC and CEC level handling, hot-plug detect and ESD at the connector.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- TPD12S016 PCB Layout Guidelines for HDMI ESDTexas Instruments, SLLA324, 2012
MIPI CSI-2
Same D-PHY rules as DSI: 100 ohm differential lanes in both TI guides, with lane-to-lane skew bounded (40 ps in TI Jacinto 7). Size the lane count and lane rate from the sensor's output format before routing.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex 5 FPGAs and SoCsAltera, 821801, 2026
- MIPI CSI-2 bandwidth calculatorGroundplane calculator
Ethernet (RGMII / RMII)
TI routes MAC-to-PHY (MII family) traces at 50 ohm single-ended, under 6 inches, matched within 20 mils for gigabit, and the PHY-side MDI pairs at 100 ohm differential. RGMII also needs a 1.5 to 2.0 ns clock-to-data delay, added on the board or inside the MAC or PHY (RGMII-ID); decide which before layout so it is not applied twice.
- Ethernet PHY PCB Design Layout ChecklistTexas Instruments, SNLA387, 2021
- PCB Design Guideline for RGMII InterfaceRenesas, R01AN6272EJ0141, 1.41, 2026
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
Board-level design guides
Impedance and timing, power, thermal and ESD guidance that applies to any board around this chip.
Impedance and timing
Every high-speed interface on the board comes down to the same two numbers: the trace impedance your stackup actually gives, and the delay each trace adds. Set the stackup with your fab first, then route to its impedance table and match lengths in time, not millimeters, where the layers differ.
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- PCB impedance calculatorGroundplane calculator
- PCB propagation delay calculatorGroundplane calculator
Power delivery
For each switching regulator, place and route the input capacitor first, keep the switching current loop small, and keep the switch node short. Give the SoC rails solid planes and decoupling at the balls, and size current-carrying copper and vias for the real load.
- Five steps to a great PCB layout for a step-down converterTexas Instruments, SLYT614, 2015
- AN-1149 Layout Guidelines for Switching Power SuppliesTexas Instruments, SNVA021, C, 2013
- AN-1229 SIMPLE SWITCHER PCB Layout GuidelinesTexas Instruments, SNVA054, C, 2013
- Buck converter calculatorGroundplane calculator
- LDO power dissipation calculatorGroundplane calculator
- PCB trace width calculatorGroundplane calculator
- Via current calculatorGroundplane calculator
Thermal
Theta-JA is measured on a JEDEC test board that carries most of the heat, so it does not transfer directly to a product board; use it to compare packages and use the psi metrics for estimates. Thermal vias under the package, copper area and copper thickness move the most heat into the board.
- Semiconductor and IC Package Thermal MetricsTexas Instruments, SPRA953, D, 2024
- AN-2020 Thermal Design By Insight, Not HindsightTexas Instruments, SNVA419, C, 2013
- Heatsink thermal resistance calculatorGroundplane calculator
- LDO power dissipation calculatorGroundplane calculator
ESD protection
Place the TVS as close to the connector as design rules allow, route from the connector to the TVS with no stub, and keep the protected IC further from the TVS than the TVS is from the connector. Choose parts by clamping performance and by capacitance low enough for the interface speed.
- ESD Protection Layout GuideTexas Instruments, SLVA680, A, 2022
- Reading and Understanding an ESD Protection Data SheetTexas Instruments, SLLA305, A
- TPD12S016 PCB Layout Guidelines for HDMI ESDTexas Instruments, SLLA324, 2012
- PCB conductor spacing calculator (IPC-2221)Groundplane calculator
Rockchip's hardware design guide
Rockchip's hardware design guide, EVB reference schematics and DDR templates come from Rockchip or an authorized agent, usually under NDA, or through your SoM vendor. We do not link copies circulating elsewhere. The vendor schematics and open designs on the Boards tab are real, shipped layouts on the RK3528 and the best public reference.
BSP, mainline and toolkits
| Area | Status | Links |
|---|---|---|
| Vendor BSP kernel | rk3528.dtsi is present in Rockchip develop-5.10, develop-6.1 and develop-6.6 branches. Board vendors ship 6.1: Armbian vendor images run 6.1.115 (ROCK 2A/2F, E24C) and 6.1.172 (E20C, NanoPi Zero2, H28K, HT2, Sige1); Radxa maintains linux-6.1-stan-rkr4.1.Checked 2026-10-13 | |
| Mainline Linux | Base device tree and Radxa E20C in 6.13; clocks, pinctrl, eMMC (SDHCI) and SARADC in 6.15; GMAC, SD/SDIO, I2C and PWM in 6.16; Mali-450 GPU (Lima), SPI, power domains and GPU OPPs in 6.17; PCIe/USB3 combo PHY, CPU OPPs up to 2016 MHz and ROCK 2A, ROCK 2F, ArmSoM Sige1 and NanoPi Zero2 in 6.18; PCIe controller in 6.19; OTP in 7.1; USB 3.0 DWC3, USB 2.0 PHY and watchdog in 7.2; HINLINK H28K in 7.3-rc. No VOP, HDMI, video decoder or audio nodes in rk3528.dtsi as of 7.3-rc7.Checked 2026-10-13 | |
| U-Boot | Mainline U-Boot documents generic-rk3528 plus ArmSoM Sige1, NanoPi Zero2, HINLINK H28K, Radxa E20C and ROCK 2A/2F, built with the rkbin BL31 (rk3528_bl31) and DDR TPL blob. Vendor boards ship Rockchip U-Boot v2017.09.Checked 2026-10-13 | |
| NPU toolkit | Not applicable: the RK3528 has no NPU.Checked 2026-10-13 | |
| Video (MPP) | Rockchip MPP has separate rk3528 and rk3528a entries: vdpu382 (vdpu382a on the A part) decoder, vepu540c encoder, JPEG and AVS decoders, and a VPU2 block. The MPP source comment says the RK3528A decoder also handles VP9, which the datasheet does not list.Checked 2026-10-13 | |
| Android | Radxa publishes Android 13 box images for the ROCK 2A (build 2024-12-30), SD card and eMMC variants.Checked 2026-10-13 | |
| Distributions | Armbian lists ROCK 2A, ROCK 2F and E24C as Standard support, and E20C, NanoPi Zero2, HINLINK H28K, HINLINK HT2 and ArmSoM Sige1 as Community; E24C also has an edge 7.1 image and NanoPi Zero2 a current 6.18 image. Radxa ships Radxa OS (Debian bookworm). FriendlyElec ships FriendlyWrt, FriendlyCore and Debian.Checked 2026-10-13 | |
| Community | Armbian forum threads cover running Armbian on RK3528 TV boxes, usually with a DTB extracted from the Android firmware; a community repo documents a config tested on Vontar DQ08 and H96 Max M1.Checked 2026-10-13 |
RK3528 on GitHub
Repositories for this chip: vendor code, mainline work, toolkits, distributions and open hardware.
- Vendor BSPradxa-build/radxa-rk3528Radxa generic RK3528 image recipe covering its ROCK 2 and E20C products. Last commit 2026-06.
- Vendor BSPfriendlyarm/sd-fuse_rk3528FriendlyELEC SD image builder for its RK3528 boards; pairs with kernel-rockchip nanopi6-v6.1.y. Last commit 2026-09.
- Kernelrockchip-linux/kernelRockchip BSP kernel; RK3528 is supported on develop-5.10 and develop-6.1. Last commit 2026-08.
- Kernelziyao233/rk3528-mainlineMainline status tracker for RK3528 kept by the developers doing the upstream Linux and U-Boot work. Last commit 2025-09.
- Kernelradxa/kernelRadxa BSP kernel; branch linux-6.1-stan-rkr1 is used for ROCK 2A, ROCK 2F and Radxa E20C. Last commit 2026-10.
- Kerneltorvalds/linuxMainline Linux has rk3528.dtsi and boards including Radxa E20C, ROCK 2A and NanoPi Zero2. Last commit 2026-10.
- Bootloaderrockchip-linux/u-bootRockchip U-Boot; next-dev has arch/arm/mach-rockchip/rk3528. Last commit 2026-08.
- Bootloaderrockchip-linux/rkbinDDR init, loaders and BL31; bin/rk35 has the rk3528 binaries, required because TF-A has no RK3528 port. Last commit 2026-08.
- Bootloaderu-boot/u-bootMainline U-Boot with generic-rk3528_defconfig plus Radxa E20C, NanoPi Zero2 and Hinlink H28K configs. Last commit 2026-10.
- Mediarockchip-linux/mppMedia Process Platform; RK3528 and RK3528A are listed in the README for hardware decode and encode. Last commit 2026-09.
- Mediaairockchip/librgaRGA 2D acceleration library with RK3528 in its supported chip list. The chip has no NPU, so no RKNN repos apply. Last commit 2026-06.
- Distributionarmbian/buildArmbian build framework with RK3528 community configs such as ArmSoM Sige1, Hinlink H28K and NanoPi Zero2. Last commit 2026-10.
- Distributionopenwrt/openwrtOpenWrt rockchip/armv8 target builds Radxa E20C, ROCK 2A, ROCK 2F and Hinlink H28K on RK3528. Last commit 2026-10.
- Distributionimmortalwrt/immortalwrtOpenWrt derivative with the same RK3528 router targets and extra Chinese market boards. Last commit 2026-10.
- DistributionMichaIng/DietPiMinimal Debian images; the NanoPi Zero2 build is the RK3528 target. Last commit 2026-10.
- Distributionophub/amlogic-s9xxx-armbianArmbian images for TV boxes and SBCs that lists RK3528 among supported Rockchip SoCs. Last commit 2026-10.
- Toolsrockchip-linux/rkdeveloptoolRockchip open source USB flashing tool for maskrom and loader mode, the Linux and macOS alternative to RKDevTool. Last commit 2025-03.
- Toolslinux-rockchip/rkflashtoolCommunity rkflashtool fork for reading and writing flash over USB in loader mode; its device table includes RK3528. Last commit 2025-09.
- Communityilyakurdyukov/rk3528-tvboxArmbian config and device trees for RK3528 TV boxes; archived, but still a good reference for cheap RK3528 hardware. Archived. Last commit 2026-03.
Every public RK3528 board
| Board | Vendor | Type | RAM | Notable I/O | Design files | Price | Buy |
|---|---|---|---|---|---|---|---|
| ROCK 2A | Radxa | SBC, Credit-card SBC, 40-pin header | 1 to 4 GB LPDDR4 | 1x GbE (PoE with HAT), 1x USB 3.0 OTG, 3x USB 2.0, PCIe 2.0 x1 FPC, HDMI 2.0, AV out, Wi-Fi 6, BT 5.4 | schematic PDF and component placement PDF (V1.2) | USD 15 for 1 GB (Arace list price, out of stock) | |
| ROCK 2F | Radxa | SBC, Compact SBC, 40-pin header | 1 to 4 GB LPDDR4 | 3x USB 2.0, PCIe 2.0 x1 FPC, HDMI 2.0 4K60, AV out, Wi-Fi 6, BT 5.4, No onboard Ethernet | schematic PDF, component placement PDF and 3D STEP (v1.01) | USD 9.90 for 1 GB (Arace list price, out of stock) | |
| E20C | Radxa | SBC, Network computer in aluminum case | 1 to 4 GB LPDDR4 | 2x GbE, 1x USB 2.0 host, USB-C debug and data, Maskrom button | schematic PDF and component placement PDF (V1.1) | ||
| E24C | Radxa | SBC, Router board, 143 x 99 mm | 1 to 4 GB LPDDR4 | 4x GbE via RTL8367RB switch, M.2 2280 NVMe (PCIe 2.1), 3x USB 2.0, HDMI 4K60, 12 V DC in | schematic PDF and component placement PDF (V1.2) | ||
| NanoPi Zero2 | FriendlyElec | SBC, 45 x 45 mm | 1 or 2 GB LPDDR4/LPDDR4X | 1x GbE, M.2 Key-E with PCIe 2.1, 1x USB 2.0 host, USB-C device, 30-pin FPC GPIO, eMMC module socket | schematic PDF and DXF outline | USD 27 for 1 GB bare board (FriendlyElec store) | |
| Sige1 | ArmSoM | SBC, 92 x 62 mm | 1 to 4 GB LPDDR4X | 1x 2.5 GbE, 1x GbE, HDMI 2.0b 4K60, 2x USB 2.0, USB-C OTG, Wi-Fi 6, BT 5.3 | schematic, 2D and SMD files (Google Drive folder) | USD 48 for 2 GB / 8 GB (ArmSoM store, out of stock) | |
| BPI-M1S | Banana Pi | SBC, 92 x 62 mm | 2 GB LPDDR4X, 8 GB eMMC | 1x 2.5 GbE, 1x GbE, HDMI 2.0b 4K60, 2x USB 2.0, USB-C OTG, Wi-Fi 6, BT 5 (RTL8852BS) | schematic, DXF and SMD files (Google Drive and Baidu) | USD 50 (Banana Pi shop, stock not shown) | |
| H28K (LinkStar H28K) | HINLINK | SBC, Travel router | 1 to 4 GB LPDDR4 | 2x GbE (RGMII RTL8211F + PCIe RTL8111H), 1x USB 2.0 | schematic PDF | USD 34.90 for 2 GB / 8 GB (Seeed Studio) | |
| HT2 | HINLINK | SBC | 2 or 4 GB LPDDR4 | 1x GbE, Dual-band Wi-Fi 6, 1x USB 3.0, 1x USB 2.0 | schematic PDF, silkscreen PDF and DTS | ||
| H29K | HINLINK | SBC | 1 or 4 GB LPDDR4 | GbE, Wi-Fi 6, 5G modem (Quectel RM500U) | enclosure drawing only | ||
| RK3528A single-board computer | Thinkcore | SBC, 56 x 65 mm | 1 to 4 GB LPDDR4 | 1x GbE, 1x USB 3.0, 3x USB 2.0, HDMI 2.0, 2.4 GHz Wi-Fi, 30-pin header |
Prices and links as checked on the dates in our data; the latest check on this page was 2026-10-13. Amazon links marked * are affiliate links; see our disclosure.
Buying the chip
Rockchip publishes no public RK3528 price or distributor list. A Rockchip-adjacent contributor on the linux-rockchip list said in July 2025 that Rockchip only supplies the RK3528A, which matches every board found.
- LCSC
- Lists RK3528A (C19779366, WBBGA-401L) from 1 piece, 119 per tray, USD 11.82 at 1+ down to USD 8.29 at 119+; out of stock when checked. Not confirmed as an authorized Rockchip channel.
- Rutronik (Europe)
- Announced in May 2020 as Rockchip authorized distributor for Europe covering the whole SoC and PMIC portfolio; RK3528 stock not confirmed.
Datasheet, TRM and design documents
Linked where they are publicly hosted; we do not rehost Rockchip documents. These are third-party documents: we are not responsible for their accuracy, availability or confidentiality status. Disclosure.
- DatasheetRockchip RK3528A DatasheetV1.2 · 2024-04-10 · hosted by FriendlyElec wiki · checked 2026-10-13
- DatasheetRockchip RK3528 DatasheetV1.0 · 2023-05-10 · hosted by Macro Group (distributor) · checked 2026-10-13
- Board schematicRadxa ROCK 2A schematic (RK3528A, discrete power, LPDDR4)V1.2 · hosted by Radxa · checked 2026-10-13
- Board schematicRadxa ROCK 2F schematicv1.01 · hosted by Radxa · checked 2026-10-13
- Board schematicRadxa E20C schematic (dual GbE)V1.1 · hosted by Radxa · checked 2026-10-13
- Board schematicRadxa E24C schematic (4-port switch, M.2 NVMe)V1.2 · hosted by Radxa · checked 2026-10-13
- Board schematicFriendlyElec NanoPi Zero2 schematic2407 · hosted by FriendlyElec wiki · checked 2026-10-13
- Board schematicHINLINK H28K debug schematichosted by HINLINK · checked 2026-10-13
- Product briefRadxa ROCK 2A Product BriefRevision 1.1 · 2024-09-04 · hosted by Radxa · checked 2026-10-13
- Otherrk3528.dtsi, mainline Linux device treev7.3-rc7 · hosted by kernel.org · checked 2026-10-13
- Otherrkbin: RK3528 DDR init, SPL, USB plug and BL31 binarieshosted by Rockchip (GitHub) · checked 2026-10-13
- OtherU-Boot Rockchip board documentation (RK3528 build steps)hosted by U-Boot project · checked 2026-10-13
- DatasheetRockchip RK3528A DatasheetV1.4 · 2025-05-12 · community mirror (rockchip.fr), not hosted by Rockchip · checked 2026-10-13
- DatasheetRockchip RK3528 DatasheetV1.4 · 2024-05-12 · community mirror (rockchip.fr), not hosted by Rockchip · checked 2026-10-13
Questions about the RK3528
Not the RK3528 itself. We have designed and brought up boards on the Rockchip RV1106, RV1126, RV1126B, RK3566, RK3568, RK3576 and RK3588, and on the Allwinner T507 and A527/T527. The work carries over: power tree, DDR and high-speed layout, bring-up and the BSP, read against this chip's own datasheet.
FriendlyElec hosts the RK3528A datasheet V1.2 (2024-04-10) on its wiki, and the distributor Macro Group hosts RK3528 V1.0 (2023-05-10). No TRM or hardware design guide is publicly hosted by Rockchip or a board vendor; schematics from Radxa, FriendlyElec and HINLINK are the practical layout reference.
The vendor-hosted datasheets (RK3528 V1.0, RK3528A V1.2) list the same CPU, GPU, video, memory and I/O. Every public board found uses the RK3528A, Rockchip MPP gives it a separate decoder entry, and mainline Linux uses the rockchip,rk3528 compatible for both. The Rev 1.4 datasheets (community mirror rockchip.fr) do differ: the RK3528 drops DDR3 and LPDDR3 support, while the RK3528A keeps DDR3/DDR3L/LPDDR3 but drops the SM2/SM3/SM4 cipher line its V1.2 datasheet listed. Both have -D part numbers with Dolby audio.
No. The datasheet lists no NPU, so RKNN does not apply. For on-device inference in this price class, look at the RK3562 or RK3566/RK3568 instead.
Partly. As of 7.3-rc7 mainline covers clocks, pinctrl, eMMC, SD/SDIO, GMAC, I2C, SPI, PWM, SARADC, the Mali-450 GPU via Lima, CPU frequency scaling, PCIe and USB 3.0. Display (VOP and HDMI) and the video decoder are not in the mainline device tree yet, so HDMI output and hardware video still need the vendor 6.1 kernel.
The RK3528 is a playback and networking chip: 4K60 HEVC decode, HDMI 2.0b, one PCIe or USB 3.0 lane and Cortex-A53 cores. The RK3566 adds Cortex-A55 cores, a Mali-G52 GPU, a 1 TOPS NPU, MIPI CSI and DSI. Choose the RK3528 when cost and video playback dominate and you need no camera, panel or NPU.
No. PCIe 2.1 x1 and USB 3.0 share one combo PHY. The datasheet notes the choice is USB 2.0 host plus USB 2.0 OTG plus PCIe, or USB 2.0 host plus USB 3.0, and Radxa documents the same limit on the ROCK 2A.
Related chips and reading
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Links and facts on this page checked 2026-10-13. Spotted something out of date? Tell us through the contact form.
Compiled from publicly available sources: datasheets, technical reference manuals, vendor product pages, schematics and source code published by their owners and third parties. We link to documents where others host them and do not host, endorse or vouch for them. Everything on these pages, including our own specs, summaries, block diagrams, comparisons, calculators and design notes, is for reference only and may contain errors or be out of date. It is provided as is, and Groundplane is not responsible for errors in it, for third-party documents, or for any design, board or decision based on it. Always check the manufacturer's current datasheet, reference manual and design guidance before you design a board. Rockchip, Allwinner, Raspberry Pi and other product names are trademarks of their owners; we are not affiliated with any of them. See our disclosure.