RK3568
Low-cost quad Cortex-A55 SoC with the most I/O in its class (PCIe 3.0 x2, two GMACs, three SATA lanes, DDR ECC), held back by a weak CPU, a 1 TOPS NPU and an 8 GB DRAM ceiling.
- CPU
- 4x A55 2.0 GHz
- GPU
- Mali-G52 2EE
- NPU
- 1 TOPS (INT8/INT16/FP16)
- Video
- 4K60 H.265/VP9/H.264 decode, 1080p60 H.265/H.264 encode
- PCIe
- PCIe 3.0 x2 (or 2x x1) + PCIe 2.1 x1
What the RK3568 is for
Right for
- Network appliances and soft routers: two RGMII GMACs plus PCIe lanes for 2.5 GbE NICs (NanoPi R5S, BPI-R2 Pro, Radxa E25)
- Small NAS and storage boxes: up to three SATA 3.0 ports or PCIe 3.0 x2 NVMe on a 4-core Arm part (mainline Linux has device trees for the QNAP TS-233 and TS-433)
- Industrial controllers that need DDR3/DDR4 ECC, 3x CAN, 10 UARTs and a -40 to 85 C part (RK3568J)
- Multi-display HMI on a budget: three display pipes across HDMI 2.0, eDP 1.3, dual MIPI DSI or LVDS
- Long-life designs: Radxa commits to CM3I supply to 2033 and ROCK 3B to 2037; Hardkernel expects to supply ODROID-M1 to 2036 or beyond
Wrong for
- CPU-bound workloads: four Cortex-A55 cores only, no big cores (RK3576 or RK3588 if you need A72/A76)
- Serious edge AI: 1 TOPS NPU, and no mainline NPU driver (rocket supports RK3588 only as of 7.3-rc7)
- Video encode above 1080p60, or any 4K encode
- Designs needing more than 8 GB DRAM or more than one 32-bit channel
- Products that must run mainline Linux with hardware 4K decode today: the RK3568 HEVC/VP9 decoder (VDPU346) is not upstream
Cost and constraints
- Every serial lane is shared: PCIe 2.1, SATA, USB 3.0 and QSGMII are muxed onto three combo PHYs, so pick lane functions at schematic time
- FCBGA636L (RK3568) or FCCSP636L (RK3568B2, RK3568J), 19 x 19 mm, 0.65 mm pitch; NanoPi R5S and R5C are 8-layer boards and the MYIR SoM is 12-layer
- BOM is the SoC (about USD 18 to 27 at LCSC in single units), RK809-5 PMIC, a separate VDD_CPU buck on vendor designs, and DRAM
- Commercial RK3568 and RK3568B2 are rated 0 to 80 C ambient in datasheet Rev 2.4 (B2 Rev 2.0 said -20 to 85 C); RK3568J -40 to 85 C but only 1.4 GHz CPU in normal mode
Inside the RK3568
Drawn by Groundplane from the datasheet rev 1.2. Not Rockchip artwork.
- DDR3/3L/4, LPDDR3/4/4X, 32-bit
- Up to 8 GB
- eMMC 5.1
- SD 3.0
- FSPI NOR/NAND
- 8-bit raw NAND
- 4x Cortex-A55, 32 KB L1 I/D
- 512 KB L3 with ECC
- Neon, FPU, crypto ext.
- Mali-G52 2EE
- 2D engine (RGA)
- 1 TOPS, INT8/INT16/FP16
- 4K60 H.265/H.264/VP9 decode
- 1080p60 H.264/H.265 encode
- JPEG codec
- IEP deinterlacer
- 8 MP ISP with HDR
- VICAP (MIPI and DVP)
- VOP2, three video ports
- HDR10/HLG, 3D-LUT
- 32-bit DDR controller with ECC
- 64 KB SRAM, 32 KB boot ROM
- TrustZone, crypto engine
- TRNG, 8 Kbit OTP
- 32-bit MCU
- PMU, 5 voltage domains
- 2x DMAC, timers, watchdog
- TSADC, SARADC
- PCIe 3.0 x2 or 2x x1
- 3 combo PHYs: PCIe 2.1 / SATA / USB3 / QSGMII
- USB 3.0 OTG + USB 3.0 host
- 2x USB 2.0 host
- 2x GMAC RGMII
- HDMI 2.0
- eDP 1.3
- 2x MIPI DSI or LVDS
- RGB, BT.1120, EBC
- MIPI CSI 4-lane, DVP
- 3x CAN
- 10x UART, 6x I2C, 4x SPI
- 16x PWM, SARADC
- I2S/TDM, PDM, SPDIF
- SDIO 3.0
Read from the documents
Each value names the document it was read from.
| CPU | 4x Cortex-A55, 32 KB L1 I/D each, 512 KB L3 with ECC, ARMv8 crypto extensions; up to 2.0 GHz | Datasheet Rev 2.4, 1.2.1, Table 3-2 |
|---|---|---|
| GPU | Mali-G52 1-Core-2EE, up to 800 MHz; OpenGL ES 1.1/2.0/3.2, Vulkan 1.0/1.1, OpenCL 2.0; 38.4 GFLOPS at 800 MHz | Datasheet Rev 2.4, 1.2.10, Table 3-2 |
| NPU | Up to 1 TOPS, INT8/INT16/FP16/BFP16, up to 1.0 GHz, own voltage domain | Datasheet Rev 1.2, 1.2.2, Table 3-2 |
| Video decode | H.265 Main10, H.264 (up to 4:2:2), VP9 Profile 0/2 up to 4096x2304@60; VP8, VC-1, MPEG-4, MPEG-2, MPEG-1 up to 1080p60 | Datasheet Rev 1.2, 1.2.7 |
| Video encode | H.264 and H.265 up to 1920x1080@60 (H.265 4096x4096@10 with tiles); JPEG encode to 8192x8192 | Datasheet Rev 1.2, 1.2.7, 1.2.8 |
| Memory | DDR3/DDR3L-2133, LPDDR3-2133, DDR4-3200, LPDDR4/LPDDR4X-3200; 32-bit, up to 8 GB; 8-bit ECC on DDR3/DDR3L/DDR4 | Datasheet Rev 1.2, 1.2.5 |
| Storage | eMMC 5.1 (HS200, CMD queue), SD 3.0, 8-bit NAND (async, ONFI, Toggle), FSPI NOR/NAND 1/2/4-bit | Datasheet Rev 1.2, 1.2.5 |
| Display | 3 video ports (4096x2304@60, 2048x1536@60, 1920x1080@60); HDMI 2.0 TX with HDCP 2.2, eDP 1.3 4-lane to 2560x1600, 2x MIPI DSI 4-lane, 2x LVDS (independent displays; dual-channel LVDS not recommended), RGB, BT.656/1120, E-ink EBC | Datasheet Rev 2.4, 1.2.12, 1.2.13 |
| Camera | MIPI CSI-2 RX, 4 lanes at 2.5 Gbps (or 2x 2-lane), 16-bit DVP; 8 MP ISP to 4096x2304 with 2-frame HDR | Datasheet Rev 1.2, 1.2.11 |
| PCIe | PCIe 3.0 PHY with 2 lanes: one x2 controller (RC or EP) or two x1 controllers (RC); plus PCIe 2.1 x1 RC on a combo PHY | Datasheet Rev 1.2, 1.2.15 |
| USB | 1x USB 3.0 OTG (DRD), 1x USB 3.0 host (both on combo PHYs), 2x USB 2.0 host | Datasheet Rev 1.2, 1.2.15 |
| Ethernet | 2x GMAC 10/100/1000, RGMII or RMII; one QSGMII/SGMII PCS on a combo PHY (two MACs usable) | Datasheet Rev 1.2, 1.2.15 |
| SATA | Up to 3x SATA 3.0 (6 Gb/s, AHCI, eSATA), each sharing a combo PHY with USB 3.0, PCIe 2.1 or QSGMII | Datasheet Rev 1.2, 1.2.15 |
| Other I/O | 3x CAN (ISO 11898-1:2003, with a datasheet caution about a protocol defect), 10x UART, 6x I2C, 4x SPI, 16x PWM, 8-ch 10-bit SARADC, 2x 8-ch I2S/TDM, 2x 2-ch I2S, PDM, SPDIF, SDIO 3.0, ISO 7816 | Datasheet Rev 2.4, 1.2.15, 1.2.16 |
| Security | TrustZone, crypto engine (AES, DES/TDES, SHA-1/2, HMAC, RSA/ECC to 4096-bit), TRNG, 8 Kbit OTP, secure boot, DDR scrambling | Datasheet Rev 1.2, 1.2.6, 1.2.16 |
| Package | RK3568: FCBGA636L, 19 x 19 mm, 0.65 mm pitch, 0.35 mm balls. RK3568B2 and RK3568J: FCCSP636L, same body and pitch | Datasheet Rev 1.2, 1.2.16, 2.1 |
| Temperature | RK3568 0 to 80 C ambient; Tj max 125 C; theta JA 14.89 C/W, theta JB 5.92 C/W, theta JC 0.24 C/W (4-layer test board) | Datasheet Rev 2.4, Table 3-1, 3-2, 4-1 |
Variants
| RK3568 | Original part, FCBGA636L. Commercial, 0 to 80 C ambient. CPU 2.0 GHz, GPU 800 MHz, NPU 1.0 GHz per Rev 2.4 (Rev 1.2 left CPU and GPU clocks as TBD). | Datasheet Rev 2.4 |
|---|---|---|
| RK3568B2 | FCCSP636L package, same 19 x 19 mm body and 0.65 mm pitch. CPU 2.0 GHz, GPU 800 MHz, NPU 1.0 GHz. 0 to 80 C ambient in Rev 2.4 (Rev 2.0 said -20 to 85 C). Feature list matches RK3568 Rev 2.4 (two LVDS, 3x CAN). Theta JA 15.89 C/W, theta JC 2.5 C/W. Used on NanoPi R5S, R5C, ODROID-M1 and Firefly Core-3568J. | Datasheet Rev 2.4 |
| RK3568J | Industrial, FCCSP636L, -40 to 85 C ambient. Normal mode: CPU 1.4 GHz, GPU 550 MHz, NPU 600 MHz. Overdrive: CPU 1.8 GHz, GPU 800 MHz, NPU 1.0 GHz, with a datasheet warning that long-term overdrive may shorten lifetime at high temperature. Theta JA 15.89 C/W, theta JC 2.5 C/W (Rev 2.4; V1.0 gave 2.43 C/W). | Datasheet Rev 2.4 |
| RK3566 (separate page) | Not pin compatible: FCCSP565L, 15.5 x 14.4 mm. One GMAC, no PCIe 3.0 (PCIe 2.1 x1 only), USB 2.0 OTG instead of USB 3.0 OTG, two SATA instead of three, no QSGMII, no DDR ECC, two displays from the same source, 4 SARADC channels. | Datasheet Rev 1.0 |
What to watch when you design with it
Size a heatsink for the RK3568 with its datasheet θJC and Tj max filled in, and download the STEP.
Power and PMIC
Rockchip pairs the RK3568 with the RK809-5 PMIC (bucks, LDOs and an audio codec). The vendor boards checked follow that: ROCK 3A and CM3I use RK809-5, and the ROCK 3A adds a TCS4525 buck for VDD_CPU with remote sense (VDD_CPU_COM). The datasheet gives separate rails for VDD_CPU (0.8 to 1.1 V), VDD_GPU, VDD_NPU, VDD_LOGIC and PMU logic, and per-PHY 0.9 V and 1.8 V analog supplies; DDR PHY VDDQ sets the DRAM type (LPDDR4X uses a separate 0.6 V VDDQL). Forlinx tells carrier designers to gate carrier rails from the SoM EXT_EN output to avoid back-powering the SoC.
Sources: Datasheet Rev 1.2, PMIC Rev 1.01, Board schematic V1.31, Product brief Revision 1.3, Other V3.3
DDR
One 32-bit controller, DDR3/DDR3L/LPDDR3 to 2133 and DDR4/LPDDR4/LPDDR4X to 3200, 8 GB address space. ECC needs DDR3/DDR3L/DDR4 and a fifth byte lane; LPDDR parts cannot use it. Every SBC and SoM checked uses LPDDR4 or LPDDR4X. Rockchip publishes DDR layout templates and length rules only in its hardware kit, which we do not link; copy a vendor board (ROCK 3A, CM3I) rather than inventing a topology.
Sources: Datasheet Rev 1.2, Board schematic V1.31, Board schematic V1.3
High-speed interfaces
Decide the combo PHY map first: PHY0 is USB 3.0 OTG or SATA0, PHY1 is USB 3.0 host, SATA1 or QSGMII, PHY2 is PCIe 2.1, SATA2 or QSGMII. The PCIe 3.0 PHY is separate and splits as x2 or two x1. Forlinx notes PCIe 2.1 is RC only, that the SoC needs an external PCIe reference clock source for the 3.0 lanes on their SoM, that CLKREQn/WAKEn pins must come from the same iomux group (M0, M1 or M2), and that USB3 traces should stay under 6 inches.
Sources: Datasheet Rev 1.2, Other V3.3
Boot and maskrom
Boot ROM order is FSPI NOR, FSPI NAND, NAND, eMMC, then SD (SDMMC0). With no valid image it falls back to USB download on the USB 3.0 OTG port, which must therefore stay routed to a connector or test pads. Vendor boards force maskrom by holding a button that disables the boot device (ROCK 3A labels it Maskrom) and use SARADC_VIN0 as the Recovery key; Forlinx documents SARADC_VIN0 as a fixed 10 k pull-up to 1.8 V that must not be left to float. SDMMC0_DET selects SD or ARM JTAG on the shared pins and must be set before power-on.
Sources: Datasheet Rev 1.2, Board schematic V1.31, Other V3.3
Thermal
Datasheet Rev 2.4 gives theta JA 14.89 C/W and theta JC 0.24 C/W for the FCBGA RK3568 on a 4-layer 114.3 x 101.6 mm test board (Rev 1.2 said 15.9 and 0.49), and theta JA 15.89 C/W, theta JC 2.5 C/W for the FCCSP RK3568B2 and RK3568J. Tj max is 125 C and the commercial RK3568 is rated 0 to 80 C ambient. Radxa rates ROCK 3A at 0 to 50 C ambient. For -40 to 85 C use RK3568J and accept 1.4 GHz in normal mode.
Sources: Datasheet Rev 2.4, Datasheet Rev 2.4, Datasheet Rev 2.4, Datasheet Rev 1.2, Product brief Revision 1.7
Gotchas
The RK3568B2 datasheet (and RK3568 Rev 2.x) carries a caution that the CAN controller has a protocol defect and peripheral compatibility must be confirmed; mainline uses a separate rk3568v2-canfd compatible with errata handling. LVDS cannot be used with dual-MIPI DSI. The RK3568 Rev 1.2 datasheet still lists max CPU clock as TBD; Rev 2.1 and later give 2.0 GHz. Rev 2.4 also says the two LVDS ports drive independent displays and dual-channel LVDS is not recommended. QSGMII supports only two of its four ports because there are only two MACs.
Sources: Datasheet Rev 1.2, Datasheet Rev 2.4, Datasheet Rev 2.0, git.kernel.org
Layout guides for the RK3568's interfaces
Public layout guidance for each interface this chip has, from vendors who publish it, plus our calculators.
LPDDR4
Point-to-point routing; TI notes that on-die termination on both ends means no board termination is needed. Byte lanes length-matched to their strobe and command/address matched to the clock, all over a solid reference plane. Impedance targets differ by vendor: TI AM62x and ADI EE-480 use 40 ohm single-ended and 80 ohm differential, Synaptics SL1680 uses 50 and 85 ohm, AMD Versal 45 and 82 ohm. Use the SoC vendor's own target and simulate.
- AM62x, AM62Lx DDR Board Design and Layout GuidelinesTexas Instruments, SPRAD06, C, 2025
- AM62Ax, AM62Px, AM62Dx LPDDR4 Board Design and Layout GuidelinesTexas Instruments, SPRAD66, B, 2024
- ADSP-2184x/ADSP-SC84x LPDDR4 Board Design GuidelinesAnalog Devices, EE-480, 1, 2026
- SL1680 General PCB Design and LPDDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001390-01, E
- DDR length matching calculatorGroundplane calculator
LPDDR4X
Same topology and matching discipline as LPDDR4, with a lower I/O voltage, so routing rules are usually published for both together. Synaptics SL1680 gives 50 ohm single-ended and 85 ohm differential for LPDDR4 and LPDDR4X; AMD Versal gives 45 and 82 ohm. Check the SoC vendor target before fixing the stackup.
- SL1680 General PCB Design and LPDDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001390-01, E
- SL1640 General PCB Design and DDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001529-01, D
- Versal Adaptive SoC PCB Design User Guide: PCB Routing Guidelines for LPDDR4/4x InterfacesAMD, UG863, 1.12, 2026
- DDR length matching calculatorGroundplane calculator
DDR4
DDR4 uses pseudo open-drain data signaling and needs a VPP supply, with command/address routed fly-by or as a balanced tree depending on device count. TI AM62x uses 40 ohm single-ended and 80 ohm differential; AMD Versal uses 50 and 90 ohm, relaxed under the BGA. Match data to strobe per byte and command/address to clock.
- AM62x, AM62Lx DDR Board Design and Layout GuidelinesTexas Instruments, SPRAD06, C, 2025
- Versal Adaptive SoC PCB Design User Guide: PCB Routing Guidelines for DDR4 InterfacesAMD, UG863, 1.12, 2026
- SL1640 General PCB Design and DDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001529-01, D
- PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex 5 FPGAs and SoCsAltera, 821801, 2026
- DDR length matching calculatorGroundplane calculator
- Via current calculatorGroundplane calculator
DDR3 / DDR3L
Fly-by command/address with termination at the end of the chain, point-to-point data lanes matched to their strobe, and a clean VREF. ST recommends 55 ohm single-ended and 100 ohm differential for DDR3 and DDR3L on STM32MP1 boards, and shows that a 4-layer board is possible with strict layer allocation.
- STM32MP1 Series DDR memory routing guidelinesSTMicroelectronics, AN5122, 3, 2019
- DDR3 Design Requirements for KeyStone DevicesTexas Instruments, SPRABI1, D, 2022
- SL2610 General PCB Design and DDR3L/DDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001629-01, A, 2025
- DDR length matching calculatorGroundplane calculator
LPDDR3
Point-to-point and normally unterminated, with command/address matched to the clock and each byte matched to its strobe. ST gives the same targets for LPDDR3 as for DDR3: 55 ohm single-ended and 100 ohm differential. Few current public guides cover LPDDR3, so treat the SoC vendor's reference layout as the stronger source.
- STM32MP1 Series DDR memory routing guidelinesSTMicroelectronics, AN5122, 3, 2019
- DDR length matching calculatorGroundplane calculator
eMMC
A single-ended bus: CLK, CMD, DAT0 to DAT7 and, for HS400, the data strobe. TI and Synaptics both route it at 50 ohm single-ended, match the group, and keep stubs short; Synaptics places a 22 or 33 ohm series resistor on CLK and STRB. At HS400 TI also checks the eMMC I/O supply impedance, not just the traces.
- AM62Px eMMC HS400 Board Design and Simulation GuidelinesTexas Instruments, SPRADP5, A, 2026
- Astra Machina Foundation Series eMMC ConfigurationSynaptics, PN 506-001594-01, D
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
SD card / SDIO
Single-ended CLK, CMD and four data lines over a solid ground plane, at constant trace width and matched length. NXP asks for clock-to-neighbor spacing greater than twice the trace height above the plane and 1.5 times for data and CMD, with 45 degree bends. UHS modes switch the I/O to 1.8 V, so a level translator often sits next to the socket.
- NVT4557/NVT4558/NVT4858 voltage-level translator layout guidelineNXP, AN13158, 1.1, 2022
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
- SD Physical Layer Simplified SpecificationSD Association, 9.10, 2023
PCIe
AC-coupled differential lanes routed with no stubs, minimal vias and back-drilled or blind vias where speed demands, with lane-to-lane skew handled by the receiver. Targets differ by guide: TI Jacinto 7 uses 85 ohm differential for lanes and 100 ohm for the reference clock, while TI's earlier SoC guide tabulates 100 ohm and, for some devices, 95 ohm. Match the target to your connector and stackup.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
USB 3.x
SuperSpeed TX and RX pairs are routed at 90 ohm differential in all three TI guides (SPRAAR7 lists 95 ohm for some devices), with AC coupling capacitors on TX, symmetric pad and via placement, and matched via counts within each pair. Keep the pairs away from the USB 2.0 pair and other aggressors, and place ESD at the connector.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
USB 2.0
One D+/D- pair at 90 ohm differential, routed in parallel for its whole length with minimal deviations at the connector and package. NXP keeps clocks and periodic signals at least 50 mils away and other signals at least 20 mils away from the pair.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
HDMI
Four TMDS pairs (three data, one clock) at 100 ohm differential, as both TI guides state, with tight intra-pair matching and as few vias as possible between the SoC and the connector. HDMI also needs 5 V supply switching, DDC and CEC level handling, hot-plug detect and ESD at the connector.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- TPD12S016 PCB Layout Guidelines for HDMI ESDTexas Instruments, SLLA324, 2012
DisplayPort / eDP
Main-link lanes are routed at 100 ohm differential in both TI guides, with no stubs and few vias; TI Jacinto 7 allows 2 vias per trace. When DisplayPort shares a USB-C connector through alt mode, the lanes run through the Type-C mux and the SuperSpeed rules apply to the shared path.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
MIPI DSI
MIPI D-PHY clock and data lanes are routed as 100 ohm differential pairs over a solid reference; TI Jacinto 7 allows no stubs, 2 vias per trace and 40 ps lane-to-lane skew. Connectors and flex cables to the panel are usually the largest discontinuity, so keep the board segment short and clean.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex 5 FPGAs and SoCsAltera, 821801, 2026
MIPI CSI-2
Same D-PHY rules as DSI: 100 ohm differential lanes in both TI guides, with lane-to-lane skew bounded (40 ps in TI Jacinto 7). Size the lane count and lane rate from the sensor's output format before routing.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex 5 FPGAs and SoCsAltera, 821801, 2026
- MIPI CSI-2 bandwidth calculatorGroundplane calculator
LVDS
Tightly coupled differential pairs terminated at the receiver in 100 ohm, with TI's EMI guide asking for 100 ohm differential traces within 5 percent. Keep pairs matched and away from other aggressors, and avoid stubs and reference plane gaps along the route to the panel connector.
- LVDS Owner's Manual: Including High-Speed CML and Signal ConditioningTexas Instruments, SNLA187, 4th edition, 2008
- High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes DesignsTexas Instruments, SNLA302, 2018
- LVDS SerDes Gen I PCB and Interconnect Design-In GuidelinesTexas Instruments, SNLA008, A, 2018
Ethernet (RGMII / RMII)
TI routes MAC-to-PHY (MII family) traces at 50 ohm single-ended, under 6 inches, matched within 20 mils for gigabit, and the PHY-side MDI pairs at 100 ohm differential. RGMII also needs a 1.5 to 2.0 ns clock-to-data delay, added on the board or inside the MAC or PHY (RGMII-ID); decide which before layout so it is not applied twice.
- Ethernet PHY PCB Design Layout ChecklistTexas Instruments, SNLA387, 2021
- PCB Design Guideline for RGMII InterfaceRenesas, R01AN6272EJ0141, 1.41, 2026
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
SATA
AC-coupled TX and RX pairs at 100 ohm differential in TI's SoC guide, routed with the same via, stub and reference plane rules as PCIe and USB 3. On Rockchip parts SATA usually shares a combo PHY with PCIe or USB 3, so the lane is routed once to whichever connector the design picks.
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
Board-level design guides
Impedance and timing, power, thermal and ESD guidance that applies to any board around this chip.
Impedance and timing
Every high-speed interface on the board comes down to the same two numbers: the trace impedance your stackup actually gives, and the delay each trace adds. Set the stackup with your fab first, then route to its impedance table and match lengths in time, not millimeters, where the layers differ.
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- PCB impedance calculatorGroundplane calculator
- PCB propagation delay calculatorGroundplane calculator
Power delivery
For each switching regulator, place and route the input capacitor first, keep the switching current loop small, and keep the switch node short. Give the SoC rails solid planes and decoupling at the balls, and size current-carrying copper and vias for the real load.
- Five steps to a great PCB layout for a step-down converterTexas Instruments, SLYT614, 2015
- AN-1149 Layout Guidelines for Switching Power SuppliesTexas Instruments, SNVA021, C, 2013
- AN-1229 SIMPLE SWITCHER PCB Layout GuidelinesTexas Instruments, SNVA054, C, 2013
- Buck converter calculatorGroundplane calculator
- LDO power dissipation calculatorGroundplane calculator
- PCB trace width calculatorGroundplane calculator
- Via current calculatorGroundplane calculator
Thermal
Theta-JA is measured on a JEDEC test board that carries most of the heat, so it does not transfer directly to a product board; use it to compare packages and use the psi metrics for estimates. Thermal vias under the package, copper area and copper thickness move the most heat into the board.
- Semiconductor and IC Package Thermal MetricsTexas Instruments, SPRA953, D, 2024
- AN-2020 Thermal Design By Insight, Not HindsightTexas Instruments, SNVA419, C, 2013
- Heatsink thermal resistance calculatorGroundplane calculator
- LDO power dissipation calculatorGroundplane calculator
ESD protection
Place the TVS as close to the connector as design rules allow, route from the connector to the TVS with no stub, and keep the protected IC further from the TVS than the TVS is from the connector. Choose parts by clamping performance and by capacitance low enough for the interface speed.
- ESD Protection Layout GuideTexas Instruments, SLVA680, A, 2022
- Reading and Understanding an ESD Protection Data SheetTexas Instruments, SLLA305, A
- TPD12S016 PCB Layout Guidelines for HDMI ESDTexas Instruments, SLLA324, 2012
- PCB conductor spacing calculator (IPC-2221)Groundplane calculator
Rockchip's hardware design guide
Rockchip's hardware design guide, EVB reference schematics and DDR templates come from Rockchip or an authorized agent, usually under NDA, or through your SoM vendor. We do not link copies circulating elsewhere. The vendor schematics and open designs on the Boards tab are real, shipped layouts on the RK3568 and the best public reference.
BSP, mainline and toolkits
| Area | Status | Links |
|---|---|---|
| Vendor BSP kernel | Rockchip kernel trees with RK3568 support on develop-5.10 (5.10.252), develop-6.1 (6.1.172, default branch), develop-6.6 and develop-6.12 (6.12.69). Board vendors ship 5.10 or 6.1 based images.Checked 2026-10-13 | |
| Mainline Linux | CPU, clocks, pinctrl, eMMC/SD and UART from 5.14 (EVB). GMAC 5.16. GPU node (Mali-G52, Panfrost) and USB 2.0 5.18. SATA, USB 3.0 and FSPI 5.19. VOP2 display driver 5.19, VOP2 and HDMI nodes plus PCIe 2.1 6.0. PCIe 3.0, MIPI DSI and Hantro VPU (H.264/VP8/MPEG-2 decode to 1080p, JPEG encode) 6.1. RGA 6.5. CAN-FD 6.12. VICAP camera capture 6.19. OTP 7.1. Not upstream as of 7.3-rc7: NPU, ISP, the 4K HEVC/VP9 decoder (VDPU346 series in review in 2026), H.264/H.265 encoder, eDP and LVDS.Checked 2026-10-13 | |
| U-Boot | Mainline U-Boot has evb-rk3568 since v2021.10, board defconfigs from v2023.04 (ROCK 3A), v2023.10 (ODROID-M1, NanoPi R5S/R5C, LubanCat 2, Radxa E25) and v2024.01 (BPI-R2 Pro, generic-rk3568). BL31 can come from upstream TF-A; DRAM init still needs the closed Rockchip TPL blob (rk3568_ddr_*.bin from rkbin).Checked 2026-10-13 | |
| NPU toolkit | RKNN-Toolkit2 lists RK3566/RK3568 as a supported platform; latest release noted in the README is v2.5.0. Runs on the vendor kernel RKNPU driver only; the mainline rocket driver matches RK3588 only.Checked 2026-10-13 | |
| Video (MPP) | Rockchip MPP is the supported path for 4K decode and H.264/H.265 encode on the vendor kernel.Checked 2026-10-13 | |
| 2D (RGA) | librga for RGA2 on the vendor kernel; mainline has the V4L2 RGA driver with an RK3568 node since 6.5.Checked 2026-10-13 | |
| Android | Android 11 images published by Firefly (ROC-RK3568-PC) and Radxa (CM3I); Radxa publishes an Android 11 image for CM3I.Checked 2026-10-13 | |
| Distributions | Armbian has board pages for ROCK 3A, NanoPi R5S, NanoPi R5C, ODROID-M1, Radxa E25, BPI-R2 Pro, Station P2 and LubanCat 2. OpenWrt 25.12.5 builds rockchip/armv8 images for RK3568 boards including ROCK 3A, ROCK 3B, Radxa E25, NanoPi R5S, NanoPi R5C, FastRhino R66S, BPI-R2 Pro and EasePi R1. Radxa ships Debian (RSDK) images for ROCK 3A/3B, CM3I and E25.Checked 2026-10-13 | |
| Community | Radxa forum, FriendlyELEC wiki, Firefly community and the linux-rockchip list are where RK3568 bring-up issues are discussed.Checked 2026-10-13 |
RK3568 on GitHub
Repositories for this chip: vendor code, mainline work, toolkits, distributions and open hardware.
- Vendor BSPfriendlyarm/sd-fuse_rk3568FriendlyELEC SD image builder for its RK3568 boards; uses kernel-rockchip nanopi6-v6.1.y and uboot-rockchip nanopi5-v2017.09. Last commit 2026-09.
- Kernelrockchip-linux/kernelRockchip BSP kernel; RK3568 is supported on develop-4.19, develop-5.10 and develop-6.1, with more than 100 rk3568 device trees. Last commit 2026-08.
- Kernelradxa/kernelRadxa BSP kernel; branch linux-5.10-gen-rkr4.1 is the ROCK 3 and CM3I kernel. Last commit 2026-10.
- Kernelhardkernel/linuxHardkernel kernel; the odroidm1-5.10.y and odroidm1-6.1.y branches support the RK3568 ODROID-M1. Last commit 2026-09.
- Kerneltorvalds/linuxMainline Linux has mature RK3568 support with about 38 device trees. Last commit 2026-10.
- Bootloaderrockchip-linux/u-bootRockchip U-Boot; next-dev holds the rk3568 SoC code shared by RK3566 and RK3568. Last commit 2026-08.
- Bootloaderrockchip-linux/rkbinDDR init, loaders and BL31; bin/rk35 has the rk3568 binaries that also boot RK3566. Last commit 2026-08.
- Bootloaderu-boot/u-bootMainline U-Boot with generic-rk3568_defconfig and board configs such as NanoPi R5S, ODROID-M1 and LubanCat 2. Last commit 2026-10.
- BootloaderTrustedFirmware-A/trusted-firmware-aRead-only mirror of TF-A; plat/rockchip/rk3568 is the open BL31 for RK3568 and RK3566. Last commit 2026-10.
- Bootloaderjaredmcneill/quartz64_uefiEDK2 UEFI firmware for RK3566 and RK3568 boards, useful for booting generic ARM64 installers. Last commit 2026-06.
- NPUairockchip/rknn-toolkit2RKNN-Toolkit2 converter and RKNPU2 runtime; supports the 1 TOPS RK3568 NPU. RKLLM does not list RK3568. Last commit 2026-10.
- NPUairockchip/rknn_model_zooReference model conversions and C demos that list RK3568 for every vision model. Last commit 2026-10.
- Mediarockchip-linux/mppMedia Process Platform; RK3566 and RK3568 are listed in the README for hardware H.264, HEVC and VP9 decode and H.264 and HEVC encode. Last commit 2026-09.
- Mediaairockchip/librgaRGA 2D acceleration library with RK3568 in its supported chip list. Last commit 2026-06.
- Distributionarmbian/buildArmbian build framework with about 25 RK3568 boards including NanoPi R5S, ROCK 3A, ODROID-M1 and Banana Pi R2 Pro. Last commit 2026-10.
- Distributionopenwrt/openwrtOpenWrt rockchip/armv8 target has about ten RK3568 router boards including NanoPi R5S and FastRhino R66S. Last commit 2026-10.
- DistributionLibreELEC/LibreELEC.tvKodi appliance OS with an RK356X device under projects/Rockchip covering RK3566 and RK3568. Last commit 2026-10.
- Open hardwareradxa/radxa-som-projectsRadxa reference carrier designs in Altium; the cm3i folder is the RK3568 industrial module. Last commit 2026-09.
- Toolsrockchip-linux/rkdeveloptoolRockchip open source USB flashing tool for maskrom and loader mode, the Linux and macOS alternative to RKDevTool. Last commit 2025-03.
- Communityblakeblackshear/frigateFrigate NVR RKNN detector lists rk3568 as a supported SoC. Last commit 2026-10.
RK3568 system on modules
Any of these can sit on a carrier board we design.
| Module | Vendor | Connector | RAM | Design files | Price | Buy |
|---|---|---|---|---|---|---|
| CM3I | Radxa | 4x 100-pin 0.4 mm pitch B2B | 1 to 8 GB LPDDR4, eMMC up to 256 GB | Module schematic PDF, pinout XLSX, DXF, 3D; IO board full Altium sources | USD 59.99 to 109.99 listed (Allnet China), out of stock | |
| LubanCat 2 IO / BTB core boards | EmbedFire | 314-pin MXM gold finger, or BTB | 1 to 8 GB, 8 to 128 GB eMMC | Carrier Allegro layout and OrCAD schematic; core board schematic PDF | ||
| Core-3568J | Firefly | MXM3.0 314-pin | 2 to 8 GB LPDDR4, 16 to 128 GB eMMC | USD 129 (Firefly store, 2 GB/32 GB); AIO-3568J kit from USD 199 | ||
| iCore-3568Q / JQ / MQ | Firefly | B2B, 1x 60-pin + 3x 80-pin | 1 to 8 GB, 8 to 128 GB eMMC | USD 179 (Firefly store, iCore-3568Q 4 GB/32 GB); JQ 1 GB/8 GB USD 169, out of stock | ||
| FET3568-C / FET3568J-C | Forlinx | B2B, 4x 80-pin 0.5 mm | 1 to 8 GB DDR4, 8 to 64 GB eMMC | hardware manual public; design files not stated on the product page | ||
| FET3568-UP4 / FET3568J-UP4 | Forlinx | 487-pin LCC + LGA (stamp hole 1.0 mm, LGA 1.27 mm) | 1 to 8 GB LPDDR4X, 8 to 64 GB eMMC | |||
| MYC-LR3568 | MYIR | LGA, 381 pins | 1 to 8 GB LPDDR4, 8 to 32 GB eMMC | USD 101 (MYIR store sample price, B2 2 GB/16 GB) | ||
| CM3568 / CM3568J | Boardcon | 202-pin, 1.0 mm pitch QFN-style edge pads | 1 to 8 GB LPDDR4, 8 to 128 GB eMMC | Hardware manual PDF and 3D model | ||
| MINI3568 / MINI3568J | Boardcon | 2x 100-pin + 1x 30-pin, 1.27 mm pitch pin headers | 2 to 8 GB with ECC, 8 to 128 GB eMMC | Hardware manual PDF and 3D model | ||
| SOM-3568J-OSM + DB3568V3 | Geniatech | OSM 1.1 Size-L, solder-down LGA | 1 to 8 GB, eMMC up to 128 GB | Carrier schematic PDF (shared RK3566/RK3568 OSM baseboard) | USD 99 (Geniatech store, 2 GB/16 GB module); USD 159 with DB3568V3 carrier | |
| SOM-3568-SMARC / SOM-3568J-SMARC | Geniatech | SMARC 2.1 (314-pin MXM edge) | 2 to 8 GB LPDDR4, 32 to 128 GB eMMC | USD 175 (Geniatech store, 4 GB/32 GB module); USD 225 with CBD-3568-SMARC carrier | ||
| SOM-3568-Q7 | Geniatech | Qseven |
Every public RK3568 board
| Board | Vendor | Type | RAM | Notable I/O | Design files | Price | Buy |
|---|---|---|---|---|---|---|---|
| ROCK 3A | Radxa | SBC, Credit-card SBC | 2, 4 or 8 GB LPDDR4 | M.2 M-key PCIe 3.0 x2, GbE (PoE with HAT), USB 3.0 OTG + USB 3.0 host, HDMI 4K60 + MIPI DSI, M.2 E-key (PCIe 2.0, SDIO) | Schematic PDF, placement map, 2D DXF, 3D | USD 30 to 60 listed (Arace), out of stock | |
| ROCK 3B | Radxa | SBC, Pico-ITX, 100 x 75 mm | 2, 4 or 8 GB LPDDR4 | 2x GbE (one PoE), M.2 M-key PCIe 3.0 x2, M.2 B-key 4G with SIM, HDMI, eDP, 2x MIPI DSI/LVDS, Industrial -40 to 85 C SKU (RK3568J) | Schematic PDF, placement map, DXF, 3D | USD 44.99 to 88.99 listed (Arace), out of stock | |
| CM3I IO Board | Radxa | Carrier, Carrier for CM3I | Full Altium schematic and layout on GitHub | USD 24.99 (Arace) | |||
| E25 | Radxa | Carrier, Router carrier with CM3I | 2x 2.5 GbE, Mini PCIe, M.2 B-key, USB 3.0, 26-pin GPIO | OrCAD schematic (DSN), PADS and Altium layout (V1.4, GitHub) | USD 89.99 to 109 listed (Allnet China), out of stock | ||
| NanoPi R5S | FriendlyELEC | SBC, 90 x 62 mm, 8-layer | 2 or 4 GB LPDDR4X (RK3568B2) | 2x 2.5 GbE (RTL8125) + 1x GbE, M.2 M-key PCIe 2.x x1, 2x USB 3.0, HDMI 2.0 | Schematic PDF and DXF | USD 128 (FriendlyELEC store, R5S-LTS 4 GB/64 GB) | |
| NanoPi R5C | FriendlyELEC | SBC, 58 x 58 mm, 8-layer | 1 to 4 GB (RK3568B2) | 2x 2.5 GbE, M.2 E-key (PCIe 2.1 x1, USB 2.0), 2x USB 3.0, HDMI 2.0 | Schematic PDF and DXF | USD 82 (FriendlyELEC store, 2 GB, no eMMC) | |
| ODROID-M1 | Hardkernel | SBC, 90 x 122 mm | 4 or 8 GB (RK3568B2) | M.2 NVMe PCIe 3.0 x2, SATA 3 with power header, GbE, 2x USB 3.0 + 2x USB 2.0, HDMI 2.0, MIPI DSI, MIPI CSI | USD 76 (Hardkernel store, 4 GB) | ||
| BPI-R2 Pro | Banana Pi | SBC, 148 x 100.5 mm router board | 2 GB LPDDR4 (4 GB optional), 16 to 64 GB eMMC | 5x GbE via switch, SATA 3.0, Mini PCIe + M.2 E-key, 2x USB 3.0, HDMI, 2x MIPI DSI, CSI | Schematic PDF and DXF (Google Drive) | USD 103 (BPI-Shop) | |
| Sige3 | ArmSoM | SBC, 92 x 62 mm | 2, 4 or 8 GB LPDDR4X (RK3568B2) | 2.5 GbE + GbE, M.2 M-key PCIe 3.0 x1, HDMI 2.0, WiFi 6, 40-pin header | Schematic, 2D and placement files (Google Drive) | ||
| Edge 2 | Mixtile | SBC, 100 x 140 mm carrier with Core 3568 SoM (5 x 5 cm) | 2 GB/16 GB or 4 GB/32 GB | M.2 PCIe 3.0 with SIM, U.2 socket (SATA or PCIe 2.0), Mini PCIe, 3x USB 3.0, RS-485 and CAN | Schematic and placement PDFs for carrier and SoM | USD 229 to 259 listed (Mixtile store), out of stock | |
| LubanCat 2 / 2N | EmbedFire | SBC, 111 x 71 mm (2), 126 x 75 mm (2N) | 1 to 8 GB | 2x GbE (2N adds 2x 2.5 GbE), M.2 PCIe 3.0 x2 (LubanCat 2), SATA (2N native), Mini PCIe with SIM, HDMI 4K60 | Schematic PDFs (all revisions), placement, DXF, STEP | ||
| ROC-RK3568-PC | Firefly | SBC | 2 to 8 GB | 2x GbE, M.2 PCIe 3.0 + SATA 3.0, HDMI 2.0, eDP, 2x MIPI DSI, 2x MIPI CSI, RS485, 2x RS232, WiFi 6 | Schematic (Firefly download page) | USD 219 (Firefly store, 4 GB/32 GB; 2 GB SKU listed at USD 139, out of stock) | |
| ROC-RK3568-PC SE | Firefly | SBC | 2 to 8 GB | USD 169 (Firefly store, 2 GB/32 GB) | |||
| Station P2 / P2S | Firefly | Dev kit, Enclosed mini PC | 2 to 8 GB | 2x GbE, M.2 NVMe + 2.5 inch SATA, WiFi 6 | USD 229 (Firefly store, Station P2S 2 GB/32 GB); original Station P2 not listed in the store | ||
| OK3568-C | Forlinx | Dev kit | HDMI 2.0, eDP, LVDS, RGB, MIPI DSI, 4-lane MIPI CSI, 12 V input | not stated on the product page | |||
| OK3568-UP4 | Forlinx | Dev kit | 2x GbE, HDMI, eDP, DSI, 2x USB 3.0, 3x MIPI CSI, PCIe 2.1 + PCIe 3.0 | not stated on the product page | |||
| MYD-LR3568 | MYIR | Dev kit | 2x GbE, 2x USB 3.0, 2x CAN, HDMI, Mini-DP, DSI, LVDS, M.2 NVMe, 40-pin header | Schematic PDF stated by MYIR, not publicly linked | USD 139 (MYIR store sample price, B2 2 GB/16 GB) | ||
| EM3568 / EM3568-AV CAM / SBC3568 | Boardcon | Dev kit, 135 x 100 mm (EM3568), 175 x 112 mm (SBC3568) | HDMI 2.0, eDP, 2x GbE, SATA, AV CAM and SBC3568 variants (camera inputs not re-checked) | hardware manual; no public schematic | |||
| XPI-3568 | Geniatech | SBC, 85 x 55 mm, Raspberry Pi footprint | 1 to 8 GB, 8 to 128 GB eMMC | RK3568 or RK3568J, GbE, HDMI 4K60, MIPI DSI and CSI, 40-pin header | None | USD 139 (Geniatech store) | |
| YY3568 | Youyeetoo | Dev kit, SoM plus carrier | USD 128.99 (SoM 2 GB/16 GB), USD 167.99 (dev kit), Youyeetoo store |
Prices and links as checked on the dates in our data; the latest check on this page was 2026-10-13. Amazon links marked * are affiliate links; see our disclosure.
Boards with published design files
| Project | Author | Files | Tool | License |
|---|---|---|---|---|
| Radxa CM3I IO Board v1.4 | Radxa | schematic (Altium SchDoc, OrCAD DSN and PDF), PCB layout (Altium PcbDoc, PADS .pcb/.asc), component placement PDF, top and bottom DXF | Altium | No license file in the repository |
| EmbedFire LubanCat 2 IO (gold finger) carrier | EmbedFire | carrier PCB layout (Allegro .brd), carrier schematic (OrCAD .DSN), Altium libraries, DXF, core board schematic, placement and pin-delay tables | Allegro | Not stated |
| EmbedFire LubanCat 2 BTB carrier | EmbedFire | carrier PCB layout (Allegro .brd), carrier schematic (OrCAD .DSN), core board schematic PDF, pin-delay and pinmux tables | Allegro | Not stated |
Buying the chip
All three variants are stocked in single units at LCSC, which is unusual for Rockchip parts and makes RK3568 prototypes practical without a Rockchip agent. Volume pricing and long-term supply go through Rockchip agents; Rockchip does not publish a distributor list we could confirm. Hardkernel expects to supply ODROID-M1 to 2036 or beyond (Rockchip guarantees RK3568B2 supply for 15 years).
- LCSC: RK3568 (C2938930)
- BGA-636 19x19, tray. USD 20.57 at qty 1, USD 19.58 at qty 10; 230 in stock on 2026-10-13. MOQ 1.
- LCSC: RK3568B2 (C3345225)
- FCCSP-636L, tray. USD 18.37 at qty 1, USD 17.07 at qty 10; 98 in stock on 2026-10-13. MOQ 1.
- LCSC: RK3568J (C18212879)
- FCCSP-636L 19x19, tray. USD 26.65 at qty 1, USD 21.93 at qty 5; 185 in stock on 2026-10-13. MOQ 1.
Datasheet, TRM and design documents
Linked where they are publicly hosted; we do not rehost Rockchip documents. These are third-party documents: we are not responsible for their accuracy, availability or confidentiality status. Disclosure.
- DatasheetRockchip RK3568 DatasheetRev 1.2 · 2021-06-01 · hosted by LCSC · checked 2026-10-13
- DatasheetRockchip RK3568B2 DatasheetRev 2.0 · 2023-09-26 · hosted by LCSC · checked 2026-10-13
- DatasheetRockchip RK3568J DatasheetV1.0 · 2022-03-04 · hosted by Radxa · checked 2026-10-13
- DatasheetRockchip RK3568J Datasheet (same revision)V1.0 · 2022-03-04 · hosted by LCSC · checked 2026-10-13
- DatasheetRockchip RK3568 Datasheet (initial release)V1.0 · 2020-12-10 · hosted by Radxa · checked 2026-10-13
- TRMRockchip RK3568 TRM Part 1V1.1 · 2021-03-01 · hosted by Radxa · checked 2026-10-13
- TRMRockchip RK3568 TRM Part 2V1.1 · 2021-03-01 · hosted by Radxa · checked 2026-10-13
- PMICRockchip RK809 DatasheetRev 1.01 · 2018-08 · hosted by Radxa · checked 2026-10-13
- DatasheetRockchip RK3566 Datasheet (for comparison)Rev 1.0 · 2020-12 · hosted by Pine64 · checked 2026-10-13
- Board schematicRadxa ROCK 3A schematic (RK3568 + RK809-5 + LPDDR4)V1.31 · hosted by Radxa · checked 2026-10-13
- Board schematicRadxa ROCK 3B schematicV1.51 · hosted by Radxa · checked 2026-10-13
- Board schematicRadxa CM3I SoM schematic (RK3568/RK3568J)V1.3 · hosted by Radxa · checked 2026-10-13
- Product briefRadxa CM3I product briefRevision 1.3 · 2024-09-04 · hosted by Radxa · checked 2026-10-13
- Product briefRadxa ROCK 3A product briefRevision 1.7 · hosted by Radxa · checked 2026-10-13
- OtherForlinx OK3568-C User's Hardware Manual (FET3568-C carrier design notes)V3.3 · 2026-03-19 · hosted by Forlinx · checked 2026-10-13
- DatasheetRockchip RK3568 DatasheetRev 2.4 · 2026-03-06 · community mirror (rockchip.fr), not hosted by Rockchip · checked 2026-10-13
- DatasheetRockchip RK3568 DatasheetRev 2.1 · 2024-06-21 · community mirror (rockchip.fr), not hosted by Rockchip · checked 2026-10-13
- DatasheetRockchip RK3568B2 DatasheetRev 2.4 · 2026-03-06 · community mirror (rockchip.fr), not hosted by Rockchip · checked 2026-10-13
- DatasheetRockchip RK3568J DatasheetRev 2.4 · 2026-03-06 · community mirror (rockchip.fr), not hosted by Rockchip · checked 2026-10-13
- TRMRockchip RK3568 TRM Part 1V1.3 · 2022-09-30 · community mirror (rockchip.fr), not hosted by Rockchip · checked 2026-10-13
- PMICRockchip RK809 DatasheetRev 2.7 · 2026-01-13 · community mirror (rockchip.fr), not hosted by Rockchip · checked 2026-10-13
Questions about the RK3568
Yes. We have designed and brought up a board on the RK3568.
LCSC hosts Rev 1.2 (June 2021) on the RK3568 part page, and the RK3568B2 Rev 2.0 (Sept 2023) on the B2 page; Radxa hosts the V1.0 datasheet, the RK3568J V1.0 datasheet and the TRM V1.1 Part 1 and Part 2. The newest RK3568 revision we know of is Rev 2.4 (March 2026), with Rev 2.1, the RK3568B2 and RK3568J Rev 2.4 and TRM Part 1 V1.3, only on the community mirror rockchip.fr.
The RK3568 adds PCIe 3.0 x2, a second GMAC, a third SATA port, USB 3.0 OTG, QSGMII, DDR ECC and a third independent display, in a larger 19 x 19 mm package. The RK3566 is 15.5 x 14.4 mm, has one GMAC, PCIe 2.1 x1 only and USB 2.0 OTG. CPU, GPU, NPU and video blocks are the same, and the two are not pin compatible.
RK3568B2 comes in FCCSP636L with the same 19 x 19 mm body and 0.65 mm pitch, rated 0 to 80 C ambient in datasheet Rev 2.4 (Rev 2.0 said -20 to 85 C), used on NanoPi R5S/R5C and ODROID-M1. RK3568J is the industrial part, -40 to 85 C, limited to 1.4 GHz CPU in normal mode and 1.8 GHz in overdrive. The original RK3568 is FCBGA636L, 0 to 80 C.
The datasheet rates it at up to 1 TOPS with INT8, INT16, FP16 and BFP16. It is used through RKNN-Toolkit2 on the vendor kernel. Mainline Linux has no RK3568 NPU support as of 7.3-rc7; the upstream rocket driver binds RK3588 only.
Good for a headless or display product: CPU, GMAC, USB 3.0, SATA, PCIe 2.1 and 3.0, HDMI and DSI through VOP2, Panfrost GPU and CAN-FD are all upstream, and 25 RK3568 board device trees are in mainline. Missing as of 7.3-rc7: NPU, ISP, 4K HEVC/VP9 hardware decode, the H.264/H.265 encoder, eDP and LVDS.
See the board table: Radxa CM3I (4x 100-pin 0.4 mm B2B), Firefly Core-3568J (314-pin MXM3.0) and iCore-3568JQ (BTB), Forlinx FET3568-C, EmbedFire LubanCat 2 core boards and Mixtile Core 3568, among others.
Related chips and reading
- RK3566HMI, e-ink readers, handhelds, CM4-class SoMs, small routers
- RK3576Edge AI boxes, HMI, NVR, Arm PC, tablets
- RK3588 / RK3588SEdge AI boxes, NVR, 8K signage, Arm desktops and servers
- RK3562Cost-down HMI, tablets, industrial gateways
- RK3399Mainline-first products, laptops, NAS, routers, HMI
- RK3528TV boxes, media players, small routers
We'll design your RK3568 board.
Tell us the interfaces, power budget and volume. An engineer replies with questions or a proposal.
Links and facts on this page checked 2026-10-13. Spotted something out of date? Tell us through the contact form.
Compiled from publicly available sources: datasheets, technical reference manuals, vendor product pages, schematics and source code published by their owners and third parties. We link to documents where others host them and do not host, endorse or vouch for them. Everything on these pages, including our own specs, summaries, block diagrams, comparisons, calculators and design notes, is for reference only and may contain errors or be out of date. It is provided as is, and Groundplane is not responsible for errors in it, for third-party documents, or for any design, board or decision based on it. Always check the manufacturer's current datasheet, reference manual and design guidance before you design a board. Rockchip, Allwinner, Raspberry Pi and other product names are trademarks of their owners; we are not affiliated with any of them. See our disclosure.