DDR length matching calculator
Converts a DQ to DQS skew budget into allowed length mismatch on your routing layer, and checks up to eight DQ nets of a byte lane against their strobe.
- Delay per length
- 6.836 ps/mm
- Effective Er
- 4.2
- Nets over budget
- 1 of 8: DQ5
- Worst skew to DQS (DQ5)
- -12.3 ps
- Spread across DQ nets
- 17.77 ps
| Net | Length, mm | Length, mil | Delay | Skew to DQS | Status |
|---|---|---|---|---|---|
| DQS (strobe) | 30.00 | 1181.1 | 205.08 ps | reference | |
| DQ0 | 29.60 | 1165.4 | 202.35 ps | -2.73 ps | Within budget |
| DQ1 | 30.20 | 1189.0 | 206.45 ps | +1.37 ps | Within budget |
| DQ2 | 30.50 | 1200.8 | 208.50 ps | +3.42 ps | Within budget |
| DQ3 | 29.90 | 1177.2 | 204.40 ps | -0.68 ps | Within budget |
| DQ4 | 30.80 | 1212.6 | 210.55 ps | +5.47 ps | Within budget |
| DQ5 | 28.20 | 1110.2 | 192.78 ps | -12.30 ps | Over budget |
| DQ6 | 30.10 | 1185.0 | 205.76 ps | +0.68 ps | Within budget |
| DQ7 | 30.30 | 1192.9 | 207.13 ps | +2.05 ps | Within budget |
How this is calculated
tpd = √Er,eff / c s/m, c = 299 792 458 m/s allowed mismatch = skew budget / tpd skew(DQn) = tpd · ( L(DQn) − L(DQS) )
- Skew budget
- You enter it. It comes from the memory controller vendor layout guide for your SoC and memory type, and differs between LPDDR4, LPDDR4X, LPDDR5 and DDR4 and between data rates. This tool does not supply vendor tolerances.
- Layer
- Stripline uses the laminate Er. Microstrip uses the Hammerstad and Jensen Er,eff from trace width, height and copper thickness, with no solder mask; a field solver result can be entered directly as Known Er,eff.
- Check
- Each DQ against the DQS of its byte lane: |skew| must not exceed the budget. Spread is the largest minus the smallest DQ delay.
- Not covered
- Package pin delay, via barrels and layer changes. Add them as equivalent length per net if your SoC vendor publishes package delays.
- Texas Instruments SCAA082A, High-Speed Layout GuidelinesNovember 2006, revised August 2017: section 1.3.1 and Table 2
- E. Hammerstad, O. Jensen, Accurate Models for Microstrip Computer-Aided Design (effective permittivity with copper thickness)IEEE MTT-S International Microwave Symposium Digest, 1980, pp. 407 to 409
- NIST, CODATA value: speed of light in vacuum, 299 792 458 m/s, exactCODATA 2022
Questions
From the layout guide of the memory controller, which is the SoC vendor. It is usually given per byte lane as DQ to DQS, separately from the address and command group to clock. Each SoC vendor sets its own figures for each memory type and data rate, so use the ones for your exact SoC, memory and speed grade.
Signals travel at different speeds on different layers. In Er 4.2 stripline 10 ps is 1.46 mm of trace; on a 0.1 mm microstrip over 0.1 mm of the same laminate with 1 oz copper, about 1.79 mm. A lane routed partly on each layer can match in length and still miss in time.
Yes, when the SoC or memory vendor publishes it. Pin to die lengths inside a BGA package differ from ball to ball. Convert each published package delay to equivalent length and add it to that net before checking the lane.
No. It checks static timing skew from trace length. Crosstalk, reflections, via stubs and power noise also close the eye, and an LPDDR4X or LPDDR5 interface at full speed should be checked with the controller vendor models.