A733
Allwinner tablet SoC with 2x Cortex-A76 and 6x Cortex-A55, a 3 TOPS NPU, 32-bit LPDDR4/4X/5 up to 16 GB and one PCIe 3.0 lane. Boards start around USD 25. The main constraint is software: it runs on Allwinner's 6.6 vendor kernel and is not yet bootable on mainline Linux.
- CPU
- 2x A76 + 6x A55, up to 2.0 GHz
- GPU
- IMG BXM-4-64 MC1
- NPU
- 3 TOPS (not on A733MX-1XX)
- Video
- 8K24 H.265/VP9/AVS2 dec, 4K30 H.265/H.264 enc
- PCIe
- PCIe 3.0 x1 (RC or EP)
What the A733 is for
Right for
- Android tablets and interactive displays, the market Allwinner designed it for: eDP 1.4b/DP 1.4 at 4K60, HDMI 2.0b at 4K60, two 4-lane MIPI DSI (DSC on DSI0), dual-link LVDS, RGB and an e-ink controller, with two independent displays
- Compact boards that need one fast lane: one PCIe 3.0 x1 port (8 GT/s, root complex or endpoint) for NVMe or a 2.5GbE controller, plus one USB 3.1 Gen2 (10 Gbps) port
- Multi-camera products: 4+4+2-lane MIPI CSI at 2 Gbps per lane, two parallel CSI ports and an ISP rated 8 MP at 60 fps per sensor online, up to four sensors
- Cost-sensitive edge AI on the vendor Linux stack: a 3 TOPS NPU (INT8) programmed through the Vivante ACUITY toolkit, on SBCs listed from USD 25 to 50
- HEVC and VP9 playback up to 8K at 24 fps
Wrong for
- Products that must run mainline Linux today: as of 7.3-rc7 only the power-domain driver, an RTC clock driver and a few bindings are upstream; there is no clock controller, pinctrl or device tree, so no board boots mainline
- Designs needing two Ethernet MACs, SATA or more than one PCIe lane: the datasheet lists one GMAC, no SATA and one PCIe 3.0 x1 controller
- Industrial temperature ranges: the A733 is rated -25 to 75 C ambient, and no industrial A733 part (T733, MR733) was found
- H.264 decode above 4K30, or any encode above 4K30
- DDR3 or DDR4 memory: only 32-bit LPDDR4, LPDDR4X and LPDDR5 are supported
Cost and constraints
- ED-FCCSP570, 15 x 15 mm, 0.27 mm balls, with 0.4 mm pitch on the outer two ball rings and 0.5 mm pitch inside: set fanout and via rules before choosing a stackup
- There is one USB 3.1 controller and two combo PHYs (one shared with eDP/DP, one shared with PCIe), so USB 3.1, DP output and PCIe have to be allocated at schematic time
- Every public A733 schematic we checked uses the X-Powers AXP318W PMIC (WBBGA-147, 8 x 8 mm, 9 bucks, 29 LDOs) from a single 5 V input
- LPDDR4/4X tops out at 1800 MHz clock in datasheet V1.01 (V0.93 said 2133 MHz); LPDDR5 at 2400 MHz (4800 MT/s)
- Datasheet and user manual pages are watermarked "Confidential" even though Radxa and Allwinner's own Tina5.0_AIOT GitLab host them publicly
Inside the A733
Drawn by Groundplane from the datasheet v0.93. Not Allwinner artwork.
- 32-bit LPDDR4/4X/LPDDR5
- UFS 3.0, 2 lanes
- eMMC 5.1 HS400
- SD 3.0 / SDIO 3.0
- SPI NOR/NAND, raw NAND
- 2x Cortex-A76, 256 KB L2 each
- 6x Cortex-A55, 128 KB L2 each
- 1 MB shared L3, up to 2.0 GHz
- RISC-V E902 up to 200 MHz
- IMG BXM-4-64 MC1
- G2D 2D engine
- 3 TOPS (HN3 and N3X only)
- 8K24 H.265/VP9/AVS2 decoder
- 4K30 H.265/H.264 encoder
- JPEG codec
- Deinterlacer (DI)
- 32-bit LPDDR4/4X/LPDDR5
- 192 KB SRAM + 512 KB shared
- Display engine, 2 outputs
- HDMI 2.0b and eDP/DP 1.4 TX
- 2x MIPI DSI, LVDS, RGB
- E-ink controller
- ISP, up to 4 sensors
- 4+4+2-lane MIPI CSI-2
- 2x parallel CSI
- Crypto engine, TRNG
- 4 Kbit eFuse, secure boot
- SMC, SPC, TZMA firewalls
- Boot ROM with FEL mode
- PPU, 8 voltage domains
- 2x 16-ch DMA, timers, RTC
- Five thermal sensors
- PCIe 3.0 x1 or USB 3.1
- USB 3.1 Gen2 or eDP/DP 1.4
- USB 2.0 DRD (FEL port)
- USB 2.0 host
- GbE MAC (RGMII/RMII)
- HDMI 2.0b TX
- 2x MIPI DSI, LVDS, RGB
- MIPI CSI 4+4+2, 2x DVP
- I2S x5, DMIC, OWA
- UART x9, TWI x16, SPI x5
Read from the documents
Each value names the document it was read from.
| CPU | 2x Cortex-A76 (64 KB L1 I/D, 256 KB L2 each) + 6x Cortex-A55 (32 KB L1 I/D, 128 KB L2 each), DynamIQ, 1 MB shared L3, up to 2.0 GHz; plus a RISC-V E902 core up to 200 MHz | Datasheet V0.93, 3.1, Table 2-1 |
|---|---|---|
| GPU | Imagination BXM-4-64 MC1; G2D 2D engine (layers up to 7680x7680) | Datasheet V0.93, 3.1, 3.4.3 |
| NPU | Up to 3 TOPS on A733MX-HN3 and A733MX-N3X; not present on A733MX-1XX | Datasheet V0.93, 3.1, Table 2-1 |
| Video decode | H.265 MP@L5.2, VP9 Profile 2 and AVS2 up to 8K at 24 fps; H.264 BP/MP/HP@L5.1 up to 4K at 30 fps; VP8, H.263, MPEG-1/2/4, AVS/AVS+, MJPEG, WMV9, VC-1 up to 1080p60 | Datasheet V0.93, 3.5.1 |
| Video encode | H.265 MP@L5.0 and H.264 HP@L4.2 up to 4K at 30 fps; MJPEG up to 4K at 15 fps | Datasheet V0.93, 3.5.2 |
| JPEG | JPEG encode up to 4K at 15 fps, decode up to 1080p60 | Datasheet V0.93, Key Features |
| ISP | Up to 4 sensors, RAW8 to RAW16; one sensor at 8 MP 60 fps linear or 8 MP 30 fps 2-frame WDR online, 24 MP 25 fps offline; 3A, 2D/3D NR, LSC, DPC, CAC, 3D-LUT; up to 16 output streams | Datasheet V0.93, 3.3.1 |
| Memory | 32-bit LPDDR4, LPDDR4X or LPDDR5, up to 16 GB; LPDDR4/4X clock up to 1800 MHz, LPDDR5 up to 2400 MHz | Datasheet V1.01, 3.2.2 |
| Storage | 2-lane UFS 3.0 (M-PHY HS-G1 to G4), 2x eMMC 5.1 with HS400, SD 3.0, SDIO 3.0, 8-bit raw NAND (ONFI/Toggle DDR 2.0), SPI flash up to octal I/O with DTR | Datasheet V0.93, 3.2.3 to 3.2.6 |
| Display | HDMI 2.0b TX up to 4K60 (HDCP 2.2, not on N3X or 1XX); eDP 1.4b/DP 1.4 up to 4K60, 1/2/4 lanes at 5.4 Gbps; 2x 4-lane MIPI DSI (dual link up to 2.5K60 or 4K45; single link 1920x1200 at 60, or 2000x1200 at 120 with DSC on DSI0 only); dual-link LVDS and RGB up to 1080p60; e-ink up to 2560x1650 at 106 Hz. Two independent or synchronous displays | Datasheet V1.01, 3.4, 3.6 |
| Camera | 3x MIPI CSI-2 (4 + 4 + 2 lanes) at up to 2 Gbps per lane; 2x parallel CSI, 8 to 16 bit, BT.656/BT.601/BT.1120 | Datasheet V0.93, 3.7 |
| PCIe | 1x PCIe 3.0 x1 (Gen1 to Gen3), root complex or endpoint (4 functions in EP mode); PHY shared with USB 3.1 | Datasheet V0.93, 3.10.2 |
| USB | 1x USB 3.1 Gen2 (10 Gbps) DRD on a combo PHY with eDP/DP or with PCIe; 1x USB 2.0 DRD; 1x USB 2.0 host | Datasheet V0.93, 3.10.1 |
| Ethernet | 1x GMAC, 10/100/1000, RGMII or RMII, IEEE 1588, EEE, jumbo frames to 16 KB | Datasheet V0.93, 3.10.3 |
| Audio | 5x I2S/PCM/TDM, 8-channel DMIC, OWA (S/PDIF) in and out; no on-chip codec | Datasheet V0.93, 3.8 |
| Security | Crypto engine (AES, SM4, SHA-2, RSA-4096, ECC-521, SM2, TRNG), 4 Kbit eFuse, secure boot, TrustZone memory and peripheral firewalls (SMC, SPC, TZMA) | Datasheet V0.93, 3.11 |
| Other I/O | 9x UART, 16x TWI, 5x SPI, 3x 10-channel PWM, 7-channel 12-bit GPADC (4 inputs reserved for boot select), LRADC, LEDC, 2x IR RX, IR TX | Datasheet V0.93, 3.10.4 to 3.10.12 |
| Process | 12 nm | Product brief V1.01, Process |
| Package | ED-FCCSP, 570 balls, 15 x 15 mm, 0.951 mm max height, 0.27 mm balls; 0.4 mm pitch on the outer two rings, 0.5 mm inside; MSL3 | Datasheet V1.01, 3.12, 7.1.1, 8.2.1 |
| Temperature | Ambient -25 to 75 C; recommended Tj -25 to 115 C; absolute max Tj 125 C | Datasheet V0.93, Table 6-1, Table 6-2 |
| Thermal | theta-JA 25.265 C/W and theta-JB 10.33 C/W (JEDEC still air, 2-layer 114.3 x 76.2 mm test board); theta-JC not given for ED-FCCSP; five on-die sensors (A76, A55, GPU, NPU, DDR) | Datasheet V0.93, Table 6-3, 3.9.8 |
Variants
| A733MX-HN3 | Full part: NPU, HDMI 2.0 TX and 6 camera BK (capture) channels. Every Radxa schematic checked (Cubie A7A, A7Z, A7S) uses it. | Datasheet V0.93 |
|---|---|---|
| A733MX-N3X | NPU and 6 BK channels, no HDMI 2.0 TX. Same ED-FCCSP570 package and CPU. | Datasheet V0.93 |
| A733MX-1XX | No NPU, no HDMI, 4 BK channels. Same package; its thermal data and package drawing were added in datasheet V0.92. | Datasheet V0.93 |
What to watch when you design with it
Power and PMIC
Every public A733 design we checked pairs the SoC with the X-Powers AXP318W: Radxa Cubie A7A, A7Z and A7S schematics, the Orange Pi 4 Pro spec table and the Jiuding X733 hardware manual. The AXP318W brief lists 9 bucks (DCDC1 3 A; DCDC2 to DCDC5 4 A with DVS; DCDC6 to DCDC9 3 A), 29 LDOs and two load switches in a WBBGA-147, 8 x 8 mm package, controlled over TWI at address 0x36. On the Cubie A7A it runs from a single 5 V rail: DCDC3 feeds VDD-CPUB (A76 cluster), DCDC5 VDD-CPUL (A55 cluster), DCDC4 VDD-GPU, DCDC2 VDD-SYS, DCDC6 and DCDC7 the DRAM I/O and PHY rails, with remote feedback lines from the SoC for the CPU, GPU and SYS rails. Datasheet V1.01 gives 0.8 V typical for VDD-CPUB, VDD-CPUL, VDD-GPU and VDD-SYS, with maxima of 1.05 V (both CPU rails), 0.96 V (GPU) and 0.84 V (SYS); V0.93 still showed TBD. The Allwinner chip-manual folder also holds AXP515, AXP517 and AXP519 datasheets; we did not confirm what role they play with the A733.
Sources: Board schematic V1.10, Board schematic V1.11, Board schematic V1.10, PMIC, Datasheet V1.01, Other Rev.01, orangepi.org
DDR
One 32-bit channel of LPDDR4, LPDDR4X or LPDDR5, up to 16 GB. Datasheet V1.01 cut the LPDDR4/4X clock limit from 2133 MHz (V0.93) to 1800 MHz; LPDDR5 stays at 2400 MHz, which matches the 4800 MT/s Orange Pi quotes for its LPDDR5 boards. The DRAM PHY supply (VCC-DRAM) is 1.1 V for LPDDR4/4X and 1.05 V for LPDDR5, and the I/O rail (VCC-DRAML) is 0.8 V, 0.6 V or 0.5 V for LPDDR4, LPDDR4X and LPDDR5. The Cubie A7A schematic shows how one PCB carries all three: resistor options switch DCDC6 and DCDC7 between the LPDDR4, LPDDR4X and LPDDR5 voltages, with LPDDR5 as the default fit. The Cubie A7Z and A7S use LPDDR4/4X and LPDDR5 respectively. DRAM training on the vendor stack is Allwinner's libdram, which Radxa tracks for this SoC (sun60iw2p1) in radxa/allwinner-dramlib; there is no open DRAM init. Allwinner's LPDDR4/4X and LPDDR5 PCB templates are part of its design kit and are not linked here.
Sources: Datasheet V1.01, Datasheet V0.93, Board schematic V1.10, Board schematic V1.11, Board schematic V1.10, github.com
High-speed interfaces
There are two SerDes combo PHYs and one USB 3.1 controller. COMB0 is a Type-C style PHY shared by USB 3.1 and 4-lane eDP 1.4b/DP 1.4; COMB1 is shared by USB 3.1 and PCIe 3.0 x1. The USB 3.1 controller attaches to one of them, so the board decides between USB 3.1 plus DP on one connector (the Cubie A7Z and Orange Pi Zero 3W bring out DP Alt mode on USB-C and put PCIe on an FPC) or a separate USB 3 port with PCIe. PCIe supports Gen1 to Gen3, x1 only, and can run as an endpoint. There is a single GMAC: Radxa pairs it with a Maxio MAE0621A PHY, Orange Pi 4 Pro with a Motorcomm YT8531CA, and the Jiuding X733 with an RTL8211F; a second port has to come over PCIe or USB. Community reports to check on your own board: an Orange Pi 4 Pro device tree workaround for NVMe drives that fail the PCIe Gen3 speed change, and an RGMII TX delay setting on the Cubie A7A vendor image that corrupts transmitted frames.
Sources: Datasheet V0.93, Board schematic V1.10, Board schematic V1.11, Other Rev.01, github.com, github.com
Boot and FEL
The boot ROM runs on A55 core 0 and samples the FEL pin first: if FEL is low it enters the mandatory upgrade (FEL) mode over USB or SD card, which is what PhoenixSuit and LiveSuit use. Otherwise it reads BOOT_MODE from eFuse. With BOOT_MODE 0 the boot medium comes from a resistor divider on GPADC0 channel 0 (BOOT-SEL): the measured value picks SD followed by raw NAND, eMMC, SPI NOR, SPI NAND or UFS, and if that fails the ROM tries the remaining media in a fixed order. With BOOT_MODE 1 three eFuse fields fix the order instead. The Cubie A7A puts a 3.9 kOhm strap on BOOT-SEL that changes with the eMMC or UFS module fitted, and brings out FEL and U-Boot keys; Orange Pi 4 Pro has a BOOT button. The A733 clock input is a 26 MHz crystal on the DCXO, plus 32.768 kHz for the RTC.
Sources: TRM V1.00, Datasheet V0.93, Board schematic V1.10, docs.radxa.com
Thermal
The datasheet gives theta-JA 25.265 C/W and theta-JB 10.33 C/W on a 2-layer JEDEC still-air board and says theta-JC is too close to zero to measure for the ED-FCCSP package. Recommended junction range is -25 to 115 C, absolute maximum 125 C, ambient -25 to 75 C. Five on-die sensors cover the A76 and A55 clusters, GPU, NPU and DDR. Radxa and Orange Pi boards provide fan headers (PWM-driven on the Cubie A7A). Allwinner has an A733 thermal design guide (V1.1, 2025-09-26) in its design kit, but we do not link it.
Sources: Datasheet V0.93, Board schematic V1.10
Gotchas
Ball size changed between datasheet revisions: V0.93 says 0.3 mm in its feature list and 0.25 mm in its pin map section, while V1.01 and Brief V1.01 say 0.27 mm throughout, so take the footprint from the current package drawing, not an older figure. The outer two ball rings are at 0.4 mm pitch. The A733MX-N3X and A733MX-1XX have no HDMI, and the 1XX has no NPU, so check the marking before copying a board design. Two pages contradict the datasheet: CNX Software and Notebookcheck list the third part as A733MX-HXX with HDMI, but the datasheet calls it A733MX-1XX with no HDMI and no NPU. Treat the brief's triple-display claim (HDMI or eDP plus two matched DSI or LVDS) as hardware only: Allwinner says the software is still under development. The vendor U-Boot that Orange Pi and Armbian build for this SoC is a 2018 branch using a T736 defconfig.
Sources: Datasheet V0.93, Datasheet V1.01, Product brief V1.01, github.com
Layout guides for the A733's interfaces
Public layout guidance for each interface this chip has, from vendors who publish it, plus our calculators.
LPDDR4
Point-to-point routing; TI notes that on-die termination on both ends means no board termination is needed. Byte lanes length-matched to their strobe and command/address matched to the clock, all over a solid reference plane. Impedance targets differ by vendor: TI AM62x and ADI EE-480 use 40 ohm single-ended and 80 ohm differential, Synaptics SL1680 uses 50 and 85 ohm, AMD Versal 45 and 82 ohm. Use the SoC vendor's own target and simulate.
- AM62x, AM62Lx DDR Board Design and Layout GuidelinesTexas Instruments, SPRAD06, C, 2025
- AM62Ax, AM62Px, AM62Dx LPDDR4 Board Design and Layout GuidelinesTexas Instruments, SPRAD66, B, 2024
- ADSP-2184x/ADSP-SC84x LPDDR4 Board Design GuidelinesAnalog Devices, EE-480, 1, 2026
- SL1680 General PCB Design and LPDDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001390-01, E
- DDR length matching calculatorGroundplane calculator
LPDDR4X
Same topology and matching discipline as LPDDR4, with a lower I/O voltage, so routing rules are usually published for both together. Synaptics SL1680 gives 50 ohm single-ended and 85 ohm differential for LPDDR4 and LPDDR4X; AMD Versal gives 45 and 82 ohm. Check the SoC vendor target before fixing the stackup.
- SL1680 General PCB Design and LPDDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001390-01, E
- SL1640 General PCB Design and DDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001529-01, D
- Versal Adaptive SoC PCB Design User Guide: PCB Routing Guidelines for LPDDR4/4x InterfacesAMD, UG863, 1.12, 2026
- DDR length matching calculatorGroundplane calculator
LPDDR5
LPDDR5 replaces the bidirectional strobe with a write clock (WCK) and an optional read strobe, so clock routing and skew budgets change from LPDDR4. AMD Versal specifies 40 ohm single-ended for command/address and data and 75 ohm differential for the clocks and read strobe.
- Versal Adaptive SoC PCB Design User Guide: PCB Routing Guidelines for LPDDR5/5x InterfacesAMD, UG863, 1.12, 2026
- PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex 5 FPGAs and SoCsAltera, 821801, 2026
- DDR length matching calculatorGroundplane calculator
eMMC
A single-ended bus: CLK, CMD, DAT0 to DAT7 and, for HS400, the data strobe. TI and Synaptics both route it at 50 ohm single-ended, match the group, and keep stubs short; Synaptics places a 22 or 33 ohm series resistor on CLK and STRB. At HS400 TI also checks the eMMC I/O supply impedance, not just the traces.
- AM62Px eMMC HS400 Board Design and Simulation GuidelinesTexas Instruments, SPRADP5, A, 2026
- Astra Machina Foundation Series eMMC ConfigurationSynaptics, PN 506-001594-01, D
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
SD card / SDIO
Single-ended CLK, CMD and four data lines over a solid ground plane, at constant trace width and matched length. NXP asks for clock-to-neighbor spacing greater than twice the trace height above the plane and 1.5 times for data and CMD, with 45 degree bends. UHS modes switch the I/O to 1.8 V, so a level translator often sits next to the socket.
- NVT4557/NVT4558/NVT4858 voltage-level translator layout guidelineNXP, AN13158, 1.1, 2022
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
- SD Physical Layer Simplified SpecificationSD Association, 9.10, 2023
UFS
UFS runs over MIPI M-PHY differential lanes, so it is routed like any multi-gigabit serial link: tight intra-pair matching, minimal vias and stubs, continuous reference planes. TI specifies 100 ohm differential for UFS lanes on Jacinto 7 and requires simulation against its channel limits.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
PCIe
AC-coupled differential lanes routed with no stubs, minimal vias and back-drilled or blind vias where speed demands, with lane-to-lane skew handled by the receiver. Targets differ by guide: TI Jacinto 7 uses 85 ohm differential for lanes and 100 ohm for the reference clock, while TI's earlier SoC guide tabulates 100 ohm and, for some devices, 95 ohm. Match the target to your connector and stackup.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
USB 3.x
SuperSpeed TX and RX pairs are routed at 90 ohm differential in all three TI guides (SPRAAR7 lists 95 ohm for some devices), with AC coupling capacitors on TX, symmetric pad and via placement, and matched via counts within each pair. Keep the pairs away from the USB 2.0 pair and other aggressors, and place ESD at the connector.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
USB 2.0
One D+/D- pair at 90 ohm differential, routed in parallel for its whole length with minimal deviations at the connector and package. NXP keeps clocks and periodic signals at least 50 mils away and other signals at least 20 mils away from the pair.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
HDMI
Four TMDS pairs (three data, one clock) at 100 ohm differential, as both TI guides state, with tight intra-pair matching and as few vias as possible between the SoC and the connector. HDMI also needs 5 V supply switching, DDC and CEC level handling, hot-plug detect and ESD at the connector.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- TPD12S016 PCB Layout Guidelines for HDMI ESDTexas Instruments, SLLA324, 2012
DisplayPort / eDP
Main-link lanes are routed at 100 ohm differential in both TI guides, with no stubs and few vias; TI Jacinto 7 allows 2 vias per trace. When DisplayPort shares a USB-C connector through alt mode, the lanes run through the Type-C mux and the SuperSpeed rules apply to the shared path.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
MIPI DSI
MIPI D-PHY clock and data lanes are routed as 100 ohm differential pairs over a solid reference; TI Jacinto 7 allows no stubs, 2 vias per trace and 40 ps lane-to-lane skew. Connectors and flex cables to the panel are usually the largest discontinuity, so keep the board segment short and clean.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex 5 FPGAs and SoCsAltera, 821801, 2026
MIPI CSI-2
Same D-PHY rules as DSI: 100 ohm differential lanes in both TI guides, with lane-to-lane skew bounded (40 ps in TI Jacinto 7). Size the lane count and lane rate from the sensor's output format before routing.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex 5 FPGAs and SoCsAltera, 821801, 2026
- MIPI CSI-2 bandwidth calculatorGroundplane calculator
LVDS
Tightly coupled differential pairs terminated at the receiver in 100 ohm, with TI's EMI guide asking for 100 ohm differential traces within 5 percent. Keep pairs matched and away from other aggressors, and avoid stubs and reference plane gaps along the route to the panel connector.
- LVDS Owner's Manual: Including High-Speed CML and Signal ConditioningTexas Instruments, SNLA187, 4th edition, 2008
- High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes DesignsTexas Instruments, SNLA302, 2018
- LVDS SerDes Gen I PCB and Interconnect Design-In GuidelinesTexas Instruments, SNLA008, A, 2018
Ethernet (RGMII / RMII)
TI routes MAC-to-PHY (MII family) traces at 50 ohm single-ended, under 6 inches, matched within 20 mils for gigabit, and the PHY-side MDI pairs at 100 ohm differential. RGMII also needs a 1.5 to 2.0 ns clock-to-data delay, added on the board or inside the MAC or PHY (RGMII-ID); decide which before layout so it is not applied twice.
- Ethernet PHY PCB Design Layout ChecklistTexas Instruments, SNLA387, 2021
- PCB Design Guideline for RGMII InterfaceRenesas, R01AN6272EJ0141, 1.41, 2026
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
Board-level design guides
Impedance and timing, power, thermal and ESD guidance that applies to any board around this chip.
Impedance and timing
Every high-speed interface on the board comes down to the same two numbers: the trace impedance your stackup actually gives, and the delay each trace adds. Set the stackup with your fab first, then route to its impedance table and match lengths in time, not millimeters, where the layers differ.
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- PCB impedance calculatorGroundplane calculator
- PCB propagation delay calculatorGroundplane calculator
Power delivery
For each switching regulator, place and route the input capacitor first, keep the switching current loop small, and keep the switch node short. Give the SoC rails solid planes and decoupling at the balls, and size current-carrying copper and vias for the real load.
- Five steps to a great PCB layout for a step-down converterTexas Instruments, SLYT614, 2015
- AN-1149 Layout Guidelines for Switching Power SuppliesTexas Instruments, SNVA021, C, 2013
- AN-1229 SIMPLE SWITCHER PCB Layout GuidelinesTexas Instruments, SNVA054, C, 2013
- Buck converter calculatorGroundplane calculator
- LDO power dissipation calculatorGroundplane calculator
- PCB trace width calculatorGroundplane calculator
- Via current calculatorGroundplane calculator
Thermal
Theta-JA is measured on a JEDEC test board that carries most of the heat, so it does not transfer directly to a product board; use it to compare packages and use the psi metrics for estimates. Thermal vias under the package, copper area and copper thickness move the most heat into the board.
- Semiconductor and IC Package Thermal MetricsTexas Instruments, SPRA953, D, 2024
- AN-2020 Thermal Design By Insight, Not HindsightTexas Instruments, SNVA419, C, 2013
- Heatsink thermal resistance calculatorGroundplane calculator
- LDO power dissipation calculatorGroundplane calculator
ESD protection
Place the TVS as close to the connector as design rules allow, route from the connector to the TVS with no stub, and keep the protected IC further from the TVS than the TVS is from the connector. Choose parts by clamping performance and by capacitance low enough for the interface speed.
- ESD Protection Layout GuideTexas Instruments, SLVA680, A, 2022
- Reading and Understanding an ESD Protection Data SheetTexas Instruments, SLLA305, A
- TPD12S016 PCB Layout Guidelines for HDMI ESDTexas Instruments, SLLA324, 2012
- PCB conductor spacing calculator (IPC-2221)Groundplane calculator
Allwinner's hardware design guide
Allwinner's hardware design guide, EVB reference schematics and DDR templates come from Allwinner or an authorized agent, usually under NDA, or through your SoM vendor. We do not link copies circulating elsewhere. The vendor schematics and open designs on the Boards tab are real, shipped layouts on the A733 and the best public reference.
BSP, mainline and toolkits
| Area | Status | Links |
|---|---|---|
| Vendor BSP kernel | Allwinner's Tina5.0 AIoT SDK on GitLab carries a linux-6.6 tree. Radxa's allwinner-aiot-linux-6.6 branch was at 6.6.98 (last commit 2026-07-30), and Orange Pi maintains orange-pi-6.6-sun60iw2. NPU, video engine, ISP and GPU drivers exist only on these vendor kernels.Checked 2026-10-13 | |
| Mainline Linux | Early bring-up only. Landed so far: PCK600 power-domain binding and driver support for A733 in 7.1, pck600 power-domain flags in 7.2, and in 7.3 the sun6i-rtc clock support for A733 plus binding compatibles for the RTC, MMC, NMI controller and SPI. As of 7.3-rc7 there is no main clock controller (CCU), no pinctrl driver and no A733 device tree, so no board boots mainline. Community out-of-tree ports exist (for example a Cubie A7S build on Linux 6.18 with A733 patches).Checked 2026-10-13 | |
| U-Boot and TF-A | Board images use Allwinner's 2018 vendor U-Boot (Orange Pi branch v2018.05-sun60iw2, built for the sun60iw2p1_t736 defconfig in Armbian). Mainline U-Boot has only the imported A733 power-domain binding header, and mainline TF-A has no sun60i platform. Community forks of U-Boot, TF-A and sunxi-tools with A733 and Orange Pi 4 Pro support are in progress.Checked 2026-10-13 | |
| NPU toolkit | The NPU is a Vivante VIP9000. Radxa documents Vivante's ACUITY toolkit for model conversion (TensorFlow, TFLite, PyTorch, Caffe, DarkNet, ONNX, Keras) and the VIPLite or Unified driver at runtime, with TIM-VX for inference. Vendor kernel only.Checked 2026-10-13 | |
| GPU | The vendor stack ships Imagination's out-of-tree pvrsrvkm kernel driver; Armbian builds it as a separate module for its sun60iw2 family. Community projects are backporting the upstream drm/imagination driver to the 6.6 vendor kernel for Mesa's PowerVR Vulkan driver.Checked 2026-10-13 | |
| Android | Radxa publishes Android 13 images: Cubie A7A builds dated 2025-08-14 (AC101 codec) and 2026-02-06 (AC101B), and a Cubie A7Z build dated 2025-09-17. Orange Pi lists Android images and Android source for the 4 Pro, Zero 3W and Zero 4.Checked 2026-10-13 | |
| Distributions | Radxa OS (Debian 11, rsdk-r6) images shared by Cubie A7A, A7Z and A7S, with separate SD/eMMC and UFS builds. Orange Pi ships Ubuntu, Debian and Orange Pi OS (Arch) for its boards. Armbian has an orangepizero3w board config plus community configs for cubie-a7z and orangepi4pro, all on the vendor 6.6 kernel. A community OpenWrt port supports the Cubie A7A and A7Z.Checked 2026-10-13 | |
| Community | linux-sunxi wiki chip page; Radxa forum; Orange Pi forum. A community index (awesome-radxa-a733) tracks NPU, GPU, video and board fixes.Checked 2026-10-13 |
Every public A733 board
| Board | Vendor | Type | RAM | Notable I/O | Design files | Price | Buy |
|---|---|---|---|---|---|---|---|
| Cubie A7A | Radxa | SBC, 85 x 56 mm | 2 to 12 GB LPDDR5 at Arace (Radxa states up to 16 GB) | GbE with PoE support, USB 3.0 host, USB 2.0 hub, PCIe 3.0 x1 connector (M.2 extension board), eMMC or UFS module socket, HDMI, MIPI DSI, MIPI CSI | Schematic PDF (V1.10), component placement PDF, 2D DXF, 3D STEP | USD 25 (Arace, 2 GB, out of stock); USD 50 for 4 GB in stock | |
| Cubie A7Z | Radxa | SBC, 65 x 30 mm (Pi Zero class) | Up to 16 GB LPDDR4/4X | USB-C 3.1 with DP Alt mode, Micro HDMI up to 4K60, PCIe 3.0 x1 FPC, 4-lane MIPI CSI, Optional UFS 3.0, Wi-Fi 6 | Schematic PDFs (V1.10, V1.11), component placement PDFs, 2D DXF, 3D STEP | ||
| Cubie A7S | Radxa | SBC | 4 to 12 GB LPDDR5 (Arace variants) | GbE, USB-C 3.2 with DP Alt mode, USB 2.0 Type-A, PCIe 3.0 connector, eMMC, Wi-Fi 6, BT 5.4 | Schematic PDF (V1.10), component placement PDF, 2D dimensions PDF and DXF, 3D STEP | USD 45 (Arace, 4 GB) | |
| Orange Pi 4 Pro | Orange Pi | SBC, 89 x 56 mm | Up to 16 GB LPDDR5 | M.2 M-key PCIe (NVMe), eMMC or UFS module, SPI flash, GbE (YT8531CA) with PoE, HDMI 2.0 4K60, 4-lane DSI, 2-lane and 4-lane CSI, USB 3.0 host, 3x USB 2.0 | Schematic PDF (V1.3.2, 2026-01-09) and top/bottom DXF on Google Drive | USD 129.99 (Amazon, 12 GB) | |
| Orange Pi Zero 3W | Orange Pi | SBC, 65 x 32 mm | Up to 16 GB LPDDR5 | Mini HDMI 2.0 4K60, USB-C 3.1 with DP Alt mode, PCIe 3.0 x1 FPC, 2x 4-lane MIPI CSI, 4-lane DSI, eMMC and UFS footprints, Wi-Fi 6 | Schematic PDF (V1.2), position diagram PDF, top/bottom DXF on Google Drive | USD 73.99 (Amazon, 4 GB) | |
| Orange Pi Zero 4 | Orange Pi | SBC, 50 x 55 mm | Up to 16 GB LPDDR5/LPDDR4X/LPDDR4 | GbE (RJ45), Mini HDMI 4K60, USB-C with USB 3.1 and DP, 16-pin FPC with PCIe 3.0 and USB 3.1, 2x 4-lane MIPI CSI | Schematic archives (V1.0 and V1.5 zip files) on Google Drive; contents not opened | USD 67.99 (Amazon, 4 GB) | |
| BPI-M8 | Banana Pi | SBC | 4 GB LPDDR5 (announced configuration) | GbE with PoE, 32 GB eMMC, UFS module support, HDMI, DP, MIPI DSI and CSI, PCIe, 40-pin GPIO | |||
| X733 development board | Jiuding (9tripod) | Dev kit | HDMI input via LT6911C bridge, HDMI 2.0 out, eDP, MIPI DSI and CSI, M.2 slot, GbE (RTL8211F), Wi-Fi (AW869A) | Hardware manual PDF (Rev.01, 2025-04-08, Chinese) |
Prices and links as checked on the dates in our data; the latest check on this page was 2026-10-13. Amazon links marked * are affiliate links; see our disclosure.
Buying the chip
We found no public distributor listing, price or MOQ for bare A733 chips. The datasheet packs the A733 119 per tray, 1190 per inner box and 7140 per carton. Radxa says Cubie A7A supply is guaranteed through 2034. Board vendors (Radxa, Orange Pi) sell boards, not chips.
Datasheet, TRM and design documents
Linked where they are publicly hosted; we do not rehost Allwinner documents. These are third-party documents: we are not responsible for their accuracy, availability or confidentiality status. Disclosure.
- DatasheetAllwinner A733 DatasheetV0.93 · 2025-06-03 · hosted by Radxa · checked 2026-10-13
- DatasheetAllwinner A733 DatasheetV1.01 · 2025-12-11 · hosted by Allwinner (Tina5.0_AIOT GitLab) · checked 2026-10-13
- TRMAllwinner A733 User ManualV1.00 · 2025-08-14 · hosted by Allwinner (Tina5.0_AIOT GitLab) · checked 2026-10-13
- Product briefAllwinner A733 BriefV1.01 · hosted by Allwinner (Tina5.0_AIOT GitLab) · checked 2026-10-13
- PMICX-Powers AXP318W Brief (a Chinese Datasheet V1.0 sits in the same folder)2025-06-12 · hosted by Allwinner (Tina5.0_AIOT GitLab) · checked 2026-10-13
- Board schematicRadxa Cubie A7A schematic (A733MX-HN3 + AXP318 + LPDDR5)V1.10 · hosted by Radxa · checked 2026-10-13
- Board schematicRadxa Cubie A7Z schematic (A733MX-HN3 + AXP318 + LPDDR4/4X)V1.11 · 2025-12-08 · hosted by Radxa · checked 2026-10-13
- Board schematicRadxa Cubie A7S schematic (A733MX-HN3 + AXP318 + LPDDR5)V1.10 · 2026-02-03 · hosted by Radxa · checked 2026-10-13
- Board schematicOrange Pi 4 Pro schematicV1.3.2 · 2026-01-09 · hosted by Orange Pi (Google Drive) · checked 2026-10-13
- Board schematicOrange Pi Zero 3W schematicV1.2 · hosted by Orange Pi (Google Drive) · checked 2026-10-13
- OtherJiuding X733 development board hardware manual (Chinese)Rev.01 · 2025-04-08 · hosted by Jiuding (9tripod) · checked 2026-10-13
Questions about the A733
Not the A733 itself. We have designed and brought up boards on the Allwinner T507 and A527/T527, and on the Rockchip RV1106, RV1126, RV1126B, RK3566, RK3568, RK3576 and RK3588. The work carries over: power tree, DDR and high-speed layout, bring-up and the BSP, read against this chip's own datasheet.
Radxa hosts datasheet V0.93 (2025-06-03) next to the Cubie A7A hardware files. The newest version we found is V1.01 (2025-12-11). Allwinner publishes it, with the A733 User Manual V1.00 (2025-08-14), the A733 Brief V1.01 and the AXP318W PMIC documents, in the chip-manual folder of its Tina5.0_AIOT GitLab release. Compared with V0.93, V1.01 lowers the LPDDR4/4X clock limit to 1800 MHz, rewrites the MIPI DSI limits and gives the ball size as 0.27 mm. All of these files carry a "Confidential" watermark.
Not yet. As of Linux 7.3-rc7 the upstream pieces are the PCK600 power-domain driver (7.1), an RTC clock driver and binding compatibles for MMC, SPI, NMI and RTC (7.3). The main clock controller, pinctrl and device trees are missing, so boards run Allwinner's 6.6 vendor kernel (Radxa at 6.6.98) with a 2018 vendor U-Boot. Mainline U-Boot and TF-A have no A733 support; community forks are working on both.
The datasheet lists three: A733MX-HN3 (NPU, HDMI, 6 capture channels), A733MX-N3X (NPU, no HDMI) and A733MX-1XX (no NPU, no HDMI, 4 capture channels). All share the 2x A76 + 6x A55 CPU at up to 2.0 GHz and the ED-FCCSP570 15 x 15 mm package. We found no T733 or MR733. Allwinner's GitLab release also carries a T736MX-HN3 datasheet (V0.91) and a T736/A733 demo board, which points to a related part; the T736 is not covered here.
The X-Powers AXP318W: 9 bucks with DVS, 29 LDOs and two switches in an 8 x 8 mm WBBGA-147, controlled over TWI. Radxa's Cubie A7A, A7Z and A7S schematics, the Orange Pi 4 Pro and the Jiuding X733 board all use it, running it from a single 5 V input. The CPU, GPU and system rails are 0.8 V typical.
The 3 TOPS NPU is a Vivante VIP9000. You convert models with Vivante's ACUITY toolkit (TensorFlow, TFLite, PyTorch, Caffe, DarkNet, ONNX, Keras) and run them through the VIPLite driver or TIM-VX on the vendor kernel. A733MX-1XX parts have no NPU. There is no mainline NPU driver.
The A733 adds two Cortex-A76 cores to six A55s, where the A527 has eight A55s. It moves from PCIe 2.1 x1 to PCIe 3.0 x1 and from USB 3.1 Gen1 (5 Gbps) to USB 3.1 Gen2 (10 Gbps). Memory is LPDDR4/4X/5 up to 16 GB, against DDR3/DDR4/LPDDR3/4/4X up to 4 GB on the A527. The NPU goes from 2 to 3 TOPS, and decode from 4K60 to 8K24 H.265/VP9. The A527 keeps two Ethernet MACs; the A733 has one. Mainline support is further along on the A523/A527 family, which has upstream device trees.
Related chips and reading
- A527 / T527Industrial HMI, dual-display terminals, gateways, robots, tablets
- RK3576Edge AI boxes, HMI, NVR, Arm PC, tablets
- RK3588 / RK3588SEdge AI boxes, NVR, 8K signage, Arm desktops and servers
- T536Power and grid terminals, PLC and motion controllers, industrial HMI, CAN gateways
- RK3568Routers, NAS, gateways, NVR, industrial HMI
- RK3566HMI, e-ink readers, handhelds, CM4-class SoMs, small routers
- H618 / H616Pi Zero class SBCs, CM4-style 3D-printer SoMs, TV boxes, retro handhelds (H700)
We'll design your A733 board.
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Links and facts on this page checked 2026-10-13. Spotted something out of date? Tell us through the contact form.
Compiled from publicly available sources: datasheets, technical reference manuals, vendor product pages, schematics and source code published by their owners and third parties. We link to documents where others host them and do not host, endorse or vouch for them. Everything on these pages, including our own specs, summaries, block diagrams, comparisons, calculators and design notes, is for reference only and may contain errors or be out of date. It is provided as is, and Groundplane is not responsible for errors in it, for third-party documents, or for any design, board or decision based on it. Always check the manufacturer's current datasheet, reference manual and design guidance before you design a board. Rockchip, Allwinner, Raspberry Pi and other product names are trademarks of their owners; we are not affiliated with any of them. See our disclosure.