A64
Low-cost quad Cortex-A53 SoC from 2015 with unusually complete mainline Linux and fully open-source boot firmware: 32-bit DDR3/LPDDR3 up to 3 GB, one GbE MAC, HDMI 1.4 4K30, 4-lane MIPI DSI, USB 2.0 only, no PCIe.
- CPU
- 4x A53 up to 1152 MHz
- GPU
- Mali-400 MP2
- NPU
- None
- Video
- 4K30 H.265 and 1080p60 H.264 dec, 1080p60 H.264 enc
- PCIe
- None
What the A64 is for
Right for
- Products that must run a mainline kernel and fully open boot chain: SPL with open DRAM init, TF-A and the crust SCP firmware are all upstream, and mainline U-Boot has supported the A64 since 2017.07
- Battery devices with a single PMIC: the AXP803 provides the CPU, DRAM and system rails plus a 2.8 A charger and fuel gauge, as on PinePhone, PineTab, Pinebook and A64-OLinuXino
- Learning or forking a complete open design: Olimex publishes full KiCad sources, Gerbers and BOMs for A64-OLinuXino (OSHWA certified) and the TERES-I laptop main board
- Panel products at up to 1920x1200: 4-lane MIPI DSI (mainline since 5.6), RGB, or single-link LVDS to 1366x768, plus HDMI 1.4 for a second output
- Headless gateways that need one GbE port and USB 2.0, at a chip price of EUR 10.25 (Olimex, single unit)
Wrong for
- Anything needing PCIe, SATA or USB 3.0: the A64 has none of them, only one USB 2.0 OTG and one USB 2.0 host (or HSIC)
- MIPI CSI cameras: the camera input is an 8-bit parallel DVP limited to 5 MP stills and 1080p30 video
- Hardware H.265 or 4K encode, or 4K H.264 decode: encode tops out at 1080p60 H.264 and H.264 decode at 1080p60
- Designs above 3 GB of RAM or with ML inference needs: the address space is 3 GB and there is no NPU
- Wide-temperature products without qualification work: the datasheet rates the A64 at -20 to +70 C ambient
Cost and constraints
- BOM is the SoC (EUR 10.25 at Olimex), an AXP803 PMIC (EUR 5.00 at Olimex), 32-bit DDR3L or LPDDR3 and an external Ethernet PHY; there is no second-source PMIC on any public board checked
- FBGA396, 15 x 15 mm at 0.65 mm pitch: FriendlyELEC states NanoPi A64 is a 6-layer board, and the A64-OLinuXino Rev H Gerbers have six copper layers
- Port D pins carry the RGB LCD bus, LVDS and the RGMII Ethernet interface, so a board gets either Ethernet or an RGB/LVDS panel, not both; MIPI DSI and HDMI are unaffected
- One DRAM channel, 32 bits wide, at up to 667 MHz (DDR3-1333) per the datasheet; mainline U-Boot defaults to 672 MHz for DDR3 boards and 552 MHz for the Pine64 LPDDR3 boards
- Bare chips: LCSC lists the A64-H (C3036453, BGA-396, tray of 119) at USD 13.58 each or USD 10.19 at 119; Olimex sells the A64 at EUR 10.25 with a 119-piece tray and 1190-piece factory pack
Inside the A64
Drawn by Groundplane from the datasheet v1.1. Not Allwinner artwork.
- 32-bit DDR3/DDR3L/LPDDR3
- eMMC 5.0
- SD / SDIO 3.0
- 8-bit raw NAND
- SPI NOR (boot)
- 4x Cortex-A53
- 32 KB L1 I/D per core
- 512 KB shared L2
- NEON, VFPv4, crypto extensions
- Mali-400 MP2
- OpenGL ES 2.0, OpenVG 1.1
- H.265 4K30 decoder
- H.264 1080p60 dec and enc
- JPEG encoder to 8192x8192
- Audio codec, 2x I2S, SPDIF
- 32-bit DRAM controller
- DDR2/DDR3/DDR3L/LPDDR2/LPDDR3
- Up to 3 GB, 667 MHz
- 112 KB boot ROM
- Display engine 2.0, 2 pipes
- HDMI 1.4 TX, HDCP 1.2
- 4-lane MIPI DSI
- RGB and LVDS TCON
- 8-bit parallel CSI
- 5 MP still, 1080p30 video
- TrustZone, secure boot
- Crypto engine, TRNG
- 2 Kbit eFuse
- CCU, 13 PLLs
- 8-channel DMA, timers, RTC
- Thermal sensors x3
- RSB link to PMIC
- GbE MAC (RGMII/RMII)
- USB 2.0 OTG
- USB 2.0 host or HSIC
- HDMI 1.4
- MIPI DSI x4, RGB, LVDS
- 8-bit DVP camera, TS in
- Analog audio, I2S x2
- UART x6, TWI x4, SPI x2
- RSB, CIR, PWM, KEYADC
Read from the documents
Each value names the document it was read from.
| CPU | 4x Cortex-A53, ARMv8 (64 and 32-bit), NEON, VFPv4, LPAE; 32 KB L1 I and 32 KB L1 D per core, 512 KB L2 | Datasheet V1.1, 2.1 |
|---|---|---|
| CPU clock | Up to 1152 MHz at 1.30 V in the mainline OPP table; Pine64 lists the same 1152 MHz. Not stated in the datasheet | Other |
| GPU | Mali-400 MP2; OpenGL ES 2.0, OpenVG 1.1 | Datasheet V1.1, 2.2 |
| Video decode | H.265 up to 4K at 30 fps or 1080p at 120 fps; H.264, MPEG-1/2/4, VP8, AVS/AVS+ up to 1080p60; VC-1 1080p30; JPEG/MJPEG 1080p30 | Datasheet V1.1, 2.6 |
| Video encode | H.264 up to 1080p60 (brief also lists 720p120) | Datasheet V1.1, 2.6 |
| JPEG | Baseline JPEG encode up to 8192x8192 | Datasheet V1.1, 2.6 |
| Memory | 32-bit DDR2, DDR3, DDR3L, LPDDR2, LPDDR3 up to 667 MHz (DDR3-1333); 2 chip selects; up to 3 GB address space | Datasheet V1.1, 2.3 |
| Storage | 3x SD/MMC controllers (eMMC 5.0, SD 2.0, SDIO 3.0; 8-bit for MMC); 8-bit raw NAND with up to 64-bit ECC per 1 KB, 2 chip selects; boot from raw NAND, eMMC, SD or SPI NOR | Datasheet V1.1, 2.3 |
| Display | HDMI 1.4 with HDCP 1.2 up to 4K30; 4-lane MIPI DSI up to 1920x1200 at 60 fps; RGB (DE/SYNC) up to 1920x1200 at 60 fps; single-link LVDS up to 1366x768 at 60 fps; display engine with main and aux pipelines | Datasheet V1.1, 2.5 |
| Camera | 8-bit parallel YUV422 CSI (DVP) with CCIR656; up to 5 MP stills and 1080p30 video. No MIPI CSI | Datasheet V1.1, 2.7 |
| PCIe | None | Datasheet V1.1, 2.9 |
| USB | 1x USB 2.0 OTG with PHY (also the FEL download port); 1x USB 2.0 EHCI/OHCI host, its PHY shared with an HSIC PHY | Datasheet V1.1, 2.9 |
| Ethernet | 1x EMAC, 10/100/1000, RGMII or RMII (external PHY), jumbo frames to 16 KB | Datasheet V1.1, 2.9 |
| Audio | On-chip codec: 2 DAC channels (100 dB SNR), capless headphone driver, 2 ADC channels (96 dB SNR), 2 differential mic inputs; 2x I2S/PCM with TDM; SPDIF (OWA) output | Datasheet V1.1, 2.8 |
| Security | TrustZone, secure boot, secure JTAG; crypto engine with AES, DES/3DES, MD5, SHA-1/224/256, HMAC, RSA up to 2048-bit, PRNG and TRNG; 2 Kbit eFuse | Datasheet V1.1, 1, 2.4 |
| Other I/O | 6x UART, 2x SPI, 4x TWI (I2C), RSB, CIR receiver, PWM, 6-bit KEYADC, TS demux with DVB-CSA 1.1, ISO7816 smart card | Datasheet V1.1, 2.4, 2.9 |
| Package | FBGA396, 15 x 15 mm, 0.65 mm ball pitch | Datasheet V1.1, 2.10, 7 |
| Temperature | Ambient -20 to +70 C; Tj max 125 C | Datasheet V1.1, Table 5-2, Table 6-1 |
| Thermal | theta-JA 21.6 C/W (JEDEC JESD51, 4-layer board); theta-JB and theta-JC listed as TBD. Three thermal sensors (one CPU, two GPU) | Datasheet V1.1, 2.4, Table 6-1 |
Variants
| A64 | Base part, positioned by Allwinner for entry-level 64-bit tablets. Quad A53, Mali-400 MP2, FBGA396 15 x 15 mm. | Product brief v1.0 |
|---|---|---|
| R18 | Same feature list, package (BGA396, 15 x 15 mm, 0.65 mm pitch) and block diagram in its brief as the A64, positioned for "intelligent hardware" with Ethernet and I2S TDM called out. Pine64 states the R18 and A64 are identical SoCs and that the R18 carries a 10-year supply commitment, and links the A64 V1.1 datasheet as the "A64/R18" datasheet. Used on PINE A64-LTS and on a Banana Pi BPI-M64 variant. | Product brief |
| H64 | OTT-box branding. The mainline commit adding the Jide Remix Mini PC describes the H64 as "just a relabelled A64", and its device tree uses the A64 dtsi with an allwinner,sun50i-h64 compatible. TF-A builds the same sun50i_a64 platform for A64, H5 and H64. No H64 datasheet or brief was found. | Other |
What to watch when you design with it
Power and PMIC
Every public A64 board checked uses the X-Powers AXP803: the mainline device trees for PINE A64, A64-LTS/SOPINE, Pinebook, PinePhone, PineTab, A64-OLinuXino, TERES-I, BPI-M64 and Orange Pi Win all bind it, and FriendlyELEC lists it for NanoPi A64. It has six DC-DC converters (DCDC2/3 can run dual-phase at 3 A each), 16 LDOs, a 2.8 A Li-ion charger, fuel gauge, and an RSB or I2C control link, in an 8 x 8 mm QFN68. The mainline Pine64 device tree maps VDD-CPUX to DCDC2 polyphased with DCDC3 (1.04 to 1.30 V), VCC-DRAM to DCDC5 (1.36 V on DDR3L boards; PinePhone runs LPDDR3 at 1.2 V), VDD-SYS to DCDC6 (1.1 V), VCC-3V3 to DCDC1, and VDD-CPUS to FLDO2 (1.1 V). The datasheet recommends VDD-CPUX 1.04 to 1.3 V, VDD-SYS 1.0 to 1.2 V, and lists 2000 mA peak on VDD-CPUX and 800 mA on VCC-DRAM. Its power-up sequence section requires the listed rails to come up together, which the AXP803 handles on the reference boards.
Sources: PMIC Rev 1.0, Datasheet V1.1, git.kernel.org, Board schematic Rev H, Board schematic v1.2b
DDR
One 32-bit channel, two chip selects, 3 GB address space, up to 667 MHz (DDR3-1333). Public boards use DDR3 or DDR3L (PINE A64/A64+, A64-OLinuXino, NanoPi A64) or LPDDR3 (A64-LTS, SOPINE, Pinebook, PinePhone, PineTab). PinePhone ships 3 GB of LPDDR3, the full address space. DRAM init is open source in mainline U-Boot (the shared sunxi DesignWare driver); defconfigs run DDR3 boards at the 672 MHz default and the Pine64 LPDDR3 boards at 552 MHz with a stock LPDDR3 timing set. No Allwinner DDR layout guide is linkable; the A64-OLinuXino KiCad project is the only fully open routed reference, with the DDR3 on a board whose Gerbers show four inner copper layers.
Sources: Datasheet V1.1, github.com, github.com, Other
High-speed interfaces
There is no SerDes: the fastest external links are DDR, RGMII, HDMI 1.4, 4-lane MIPI DSI and USB 2.0. The RGMII signals are a pin function of Port D (PD8 to PD19), the same pins as the RGB LCD data bus and the LVDS pairs, so Ethernet and an RGB or LVDS panel cannot be used at the same time. Olimex documents the consequence on A64-OLinuXino: to use its LCD connector the Ethernet PHY must be held in reset with the PHYRST1 jumper. Plan MIPI DSI or HDMI for the display if the product needs wired Ethernet. The second USB host port shares its PHY with HSIC, and Pine64 and Olimex boards add a USB hub when they need more host ports.
Sources: Datasheet V1.1, olimex.com
Boot and FEL
The boot ROM (112 KB) boots from raw NAND, eMMC, SD/TF or SPI NOR and supports USB download through the OTG port. Ball F17 is the FEL (UBOOT) input: held low at reset it forces USB download mode. Community testing on Pine64 and the Remix Mini found the order SD (SMHC0), then eMMC (SMHC2), then SPI NOR, then FEL. Olimex brings the pin to a UBOOT button. Mainline U-Boot builds an AArch64 SPL with open DRAM init, then TF-A (PLAT=sun50i_a64) as BL31 and optionally crust as SCP firmware; FEL booting needs a 32-bit SPL because the boot ROM runs in AArch32, and linux-sunxi documents that flow with sunxi-fel.
Sources: Datasheet V1.1, linux-sunxi.org, linux-sunxi.org, docs.u-boot.org, Board schematic Rev H
Thermal
The datasheet gives theta-JA 21.6 C/W on a JEDEC 4-layer board, Tj max 125 C and an ambient range of -20 to +70 C; theta-JB and theta-JC are TBD. Three on-chip sensors (one for the CPU, two for the GPU) have over-temperature interrupts; mainline describes them and the CPU OPP table since 5.6. Olimex sells -IND variants of A64-OLinuXino with components rated -40 to +85 C, but the A64 datasheet itself only covers -20 to +70 C ambient.
Sources: Datasheet V1.1, Other, olimex.com
Gotchas
The A64 generic timer is unstable: mainline carries the SUN50I_ERRATUM_UNKNOWN1 workaround (since 5.1), enabled by the allwinner,erratum-unknown1 property in the SoC dtsi, so a custom kernel must keep it. The Cortex-A53 cores are affected by erratum 843419 in AArch64 state (linux-sunxi). Port D muxes RGMII with RGB and LVDS (see above). Pine64 warns that SOPINE modules on the Clusterboard will try to charge the RTC backup cells, so primary AA cells must not be fitted without modification. The A64 has no MIPI CSI receiver; PinePhone cameras use the parallel CSI bus.
Sources: git.kernel.org, linux-sunxi.org, Datasheet V1.1, pine64.org
Layout guides for the A64's interfaces
Public layout guidance for each interface this chip has, from vendors who publish it, plus our calculators.
DDR3 / DDR3L
Fly-by command/address with termination at the end of the chain, point-to-point data lanes matched to their strobe, and a clean VREF. ST recommends 55 ohm single-ended and 100 ohm differential for DDR3 and DDR3L on STM32MP1 boards, and shows that a 4-layer board is possible with strict layer allocation.
- STM32MP1 Series DDR memory routing guidelinesSTMicroelectronics, AN5122, 3, 2019
- DDR3 Design Requirements for KeyStone DevicesTexas Instruments, SPRABI1, D, 2022
- SL2610 General PCB Design and DDR3L/DDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001629-01, A, 2025
- DDR length matching calculatorGroundplane calculator
LPDDR3
Point-to-point and normally unterminated, with command/address matched to the clock and each byte matched to its strobe. ST gives the same targets for LPDDR3 as for DDR3: 55 ohm single-ended and 100 ohm differential. Few current public guides cover LPDDR3, so treat the SoC vendor's reference layout as the stronger source.
- STM32MP1 Series DDR memory routing guidelinesSTMicroelectronics, AN5122, 3, 2019
- DDR length matching calculatorGroundplane calculator
eMMC
A single-ended bus: CLK, CMD, DAT0 to DAT7 and, for HS400, the data strobe. TI and Synaptics both route it at 50 ohm single-ended, match the group, and keep stubs short; Synaptics places a 22 or 33 ohm series resistor on CLK and STRB. At HS400 TI also checks the eMMC I/O supply impedance, not just the traces.
- AM62Px eMMC HS400 Board Design and Simulation GuidelinesTexas Instruments, SPRADP5, A, 2026
- Astra Machina Foundation Series eMMC ConfigurationSynaptics, PN 506-001594-01, D
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
SD card / SDIO
Single-ended CLK, CMD and four data lines over a solid ground plane, at constant trace width and matched length. NXP asks for clock-to-neighbor spacing greater than twice the trace height above the plane and 1.5 times for data and CMD, with 45 degree bends. UHS modes switch the I/O to 1.8 V, so a level translator often sits next to the socket.
- NVT4557/NVT4558/NVT4858 voltage-level translator layout guidelineNXP, AN13158, 1.1, 2022
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
- SD Physical Layer Simplified SpecificationSD Association, 9.10, 2023
PCIe
AC-coupled differential lanes routed with no stubs, minimal vias and back-drilled or blind vias where speed demands, with lane-to-lane skew handled by the receiver. Targets differ by guide: TI Jacinto 7 uses 85 ohm differential for lanes and 100 ohm for the reference clock, while TI's earlier SoC guide tabulates 100 ohm and, for some devices, 95 ohm. Match the target to your connector and stackup.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
USB 2.0
One D+/D- pair at 90 ohm differential, routed in parallel for its whole length with minimal deviations at the connector and package. NXP keeps clocks and periodic signals at least 50 mils away and other signals at least 20 mils away from the pair.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
HDMI
Four TMDS pairs (three data, one clock) at 100 ohm differential, as both TI guides state, with tight intra-pair matching and as few vias as possible between the SoC and the connector. HDMI also needs 5 V supply switching, DDC and CEC level handling, hot-plug detect and ESD at the connector.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- TPD12S016 PCB Layout Guidelines for HDMI ESDTexas Instruments, SLLA324, 2012
MIPI DSI
MIPI D-PHY clock and data lanes are routed as 100 ohm differential pairs over a solid reference; TI Jacinto 7 allows no stubs, 2 vias per trace and 40 ps lane-to-lane skew. Connectors and flex cables to the panel are usually the largest discontinuity, so keep the board segment short and clean.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex 5 FPGAs and SoCsAltera, 821801, 2026
MIPI CSI-2
Same D-PHY rules as DSI: 100 ohm differential lanes in both TI guides, with lane-to-lane skew bounded (40 ps in TI Jacinto 7). Size the lane count and lane rate from the sensor's output format before routing.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex 5 FPGAs and SoCsAltera, 821801, 2026
- MIPI CSI-2 bandwidth calculatorGroundplane calculator
LVDS
Tightly coupled differential pairs terminated at the receiver in 100 ohm, with TI's EMI guide asking for 100 ohm differential traces within 5 percent. Keep pairs matched and away from other aggressors, and avoid stubs and reference plane gaps along the route to the panel connector.
- LVDS Owner's Manual: Including High-Speed CML and Signal ConditioningTexas Instruments, SNLA187, 4th edition, 2008
- High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes DesignsTexas Instruments, SNLA302, 2018
- LVDS SerDes Gen I PCB and Interconnect Design-In GuidelinesTexas Instruments, SNLA008, A, 2018
Ethernet (RGMII / RMII)
TI routes MAC-to-PHY (MII family) traces at 50 ohm single-ended, under 6 inches, matched within 20 mils for gigabit, and the PHY-side MDI pairs at 100 ohm differential. RGMII also needs a 1.5 to 2.0 ns clock-to-data delay, added on the board or inside the MAC or PHY (RGMII-ID); decide which before layout so it is not applied twice.
- Ethernet PHY PCB Design Layout ChecklistTexas Instruments, SNLA387, 2021
- PCB Design Guideline for RGMII InterfaceRenesas, R01AN6272EJ0141, 1.41, 2026
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
Board-level design guides
Impedance and timing, power, thermal and ESD guidance that applies to any board around this chip.
Impedance and timing
Every high-speed interface on the board comes down to the same two numbers: the trace impedance your stackup actually gives, and the delay each trace adds. Set the stackup with your fab first, then route to its impedance table and match lengths in time, not millimeters, where the layers differ.
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- PCB impedance calculatorGroundplane calculator
- PCB propagation delay calculatorGroundplane calculator
Power delivery
For each switching regulator, place and route the input capacitor first, keep the switching current loop small, and keep the switch node short. Give the SoC rails solid planes and decoupling at the balls, and size current-carrying copper and vias for the real load.
- Five steps to a great PCB layout for a step-down converterTexas Instruments, SLYT614, 2015
- AN-1149 Layout Guidelines for Switching Power SuppliesTexas Instruments, SNVA021, C, 2013
- AN-1229 SIMPLE SWITCHER PCB Layout GuidelinesTexas Instruments, SNVA054, C, 2013
- Buck converter calculatorGroundplane calculator
- LDO power dissipation calculatorGroundplane calculator
- PCB trace width calculatorGroundplane calculator
- Via current calculatorGroundplane calculator
Thermal
Theta-JA is measured on a JEDEC test board that carries most of the heat, so it does not transfer directly to a product board; use it to compare packages and use the psi metrics for estimates. Thermal vias under the package, copper area and copper thickness move the most heat into the board.
- Semiconductor and IC Package Thermal MetricsTexas Instruments, SPRA953, D, 2024
- AN-2020 Thermal Design By Insight, Not HindsightTexas Instruments, SNVA419, C, 2013
- Heatsink thermal resistance calculatorGroundplane calculator
- LDO power dissipation calculatorGroundplane calculator
ESD protection
Place the TVS as close to the connector as design rules allow, route from the connector to the TVS with no stub, and keep the protected IC further from the TVS than the TVS is from the connector. Choose parts by clamping performance and by capacitance low enough for the interface speed.
- ESD Protection Layout GuideTexas Instruments, SLVA680, A, 2022
- Reading and Understanding an ESD Protection Data SheetTexas Instruments, SLLA305, A
- TPD12S016 PCB Layout Guidelines for HDMI ESDTexas Instruments, SLLA324, 2012
- PCB conductor spacing calculator (IPC-2221)Groundplane calculator
Allwinner's hardware design guide
Allwinner's hardware design guide, EVB reference schematics and DDR templates come from Allwinner or an authorized agent, usually under NDA, or through your SoM vendor. We do not link copies circulating elsewhere. The vendor schematics and open designs on the Boards tab are real, shipped layouts on the A64 and the best public reference.
BSP, mainline and toolkits
| Area | Status | Links |
|---|---|---|
| Vendor BSP kernel | Allwinner's original BSP (lichee) is a Linux 3.10 kernel with a 32-bit U-Boot 2014.07 and binary blobs for DRAM, HDMI and NAND, per linux-sunxi. Board vendors carry later forks, for example Banana Pi's BPI-M64-bsp-4.4 (Linux 4.4, last pushed 2020-09-07). No current Allwinner BSP for the A64 was found; the mainline kernel is the practical choice.Checked 2026-10-13 | |
| Mainline Linux | SoC dtsi landed in 4.10; MMC and USB in 4.11; the RSB PMIC bus in 4.13; EMAC Ethernet in 4.15; display engine 2 in 4.19; HDMI and LVDS in 4.20; Mali-400 GPU node and the cedrus video engine node in 5.0, with the Lima GPU driver in 5.2; parallel CSI and the timer erratum workaround in 5.1; crypto engine in 5.5; MIPI DSI, thermal sensors and the CPU OPP table (to 1152 MHz) in 5.6; deinterlacer and PinePhone 1.0/1.1 and PineTab device trees in 5.7; PinePhone 1.2 in 5.9; the H64 Remix Mini PC in 6.9. Cedrus (still in drivers/staging) decodes MPEG-2, H.264, H.265 (A64 since 5.5) and VP8; there is no mainline hardware encoder. 19 A64 or H64 board device trees are upstream as of 7.3-rc7.Checked 2026-10-13 | |
| U-Boot | Mainline U-Boot fully supports the A64 since 2017.07 (basic support 2016.05, DRAM init and SPL 2017.03, ATF loading 2017.07, per linux-sunxi). Current master (latest tag v2026.10) has defconfigs for A64-OLinuXino (and eMMC), Amarula A64-Relic, BPI-M64, NanoPi A64, Oceanic 5205 5inMFD, Orange Pi Win, PINE A64+, A64-LTS, SOPINE baseboard, Pinebook, PinePhone, PineTab and TERES-I. DRAM init is open source; no vendor blob is needed.Checked 2026-10-13 | |
| TF-A and SCP firmware | Upstream Trusted Firmware-A builds PLAT=sun50i_a64 for A64, H5 and H64. crust (latest tag v0.6, 2023-09-02) is open SCP firmware for the AR100 OpenRISC core and lists the A64 as production/stable, providing suspend and power-off handling.Checked 2026-10-13 | |
| Android | Vendor images only. Olimex publishes Android images for A64-OLinuXino (HDMI or 7-inch LCD) and TERES-I; Banana Pi publishes Android 7 and Android 8.1 source trees for the A64. The A64 brief states Android 5.0 on Linux 3.10 at launch.Checked 2026-10-13 | |
| Distributions | Armbian has board pages for Pine64 (standard support) and for SOPINE, BPI-M64, Orange Pi Win and Pinebook A64 (community maintained). Olimex ships Olimage (Debian-based) images for A64-OLinuXino. Mobian builds Debian images for the PinePhone. OpenWrt has a Pine64 table-of-hardware page.Checked 2026-10-13 | |
| Community | linux-sunxi wiki and IRC/mailing list (register guide, BROM and FEL notes, device pages), Pine64 documentation and forum, Olimex forum and GitHub.Checked 2026-10-13 |
A64 system on modules
Any of these can sit on a carrier board we design.
| Module | Vendor | Connector | RAM | Design files | Price | Buy |
|---|---|---|---|---|---|---|
| SOPINE A64 | Pine64 | DDR3 SO-DIMM edge (204-pin) | 2 GB LPDDR3 | Module schematic PDF (ver 0.9) and pin assignment PDF (ver 1.0) | USD 32.99 (Pine64 store) |
Every public A64 board
| Board | Vendor | Type | RAM | Notable I/O | Design files | Price | Buy |
|---|---|---|---|---|---|---|---|
| A64-OLinuXino | Olimex | SBC, 90.0 x 62.5 mm | 1 or 2 GB DDR3L | GbE, HDMI, 40-pin LCD, MIPI DSI, USB OTG, USB host, HSIC header, Li-Po charger (AXP803), UEXT, 40-pin GPIO | Full KiCad project (schematic, PCB) for Rev A, B and H, Gerbers and drill (Rev H), BOMs per variant, schematic PDFs, STEP/WRL models | EUR 45.06 (Olimex, A64-OLinuXino-1G) | |
| TERES-I DIY laptop (TERES-A64) | Olimex | Dev kit, Laptop kit, 11.6 in 1366x768 | 16 GB eMMC, 9500 mAh battery, Keyboard controller board (AVR) | KiCad sources for the A64 main board (Rev.B with Gerbers, Rev.C with PDF), IO, touch-button and other boards | EUR 280.00 (Olimex, in stock) | ||
| PINE A64-LTS V2 (R18) | Pine64 | SBC | 2 GB LPDDR3 | GbE (Motorcomm YT8511C on V2), 128 Mb SPI flash, optional eMMC module, HDMI, MIPI DSI, CSI, Pi-2 and Euler GPIO headers | Schematic PDF (2018-01-30); connector pin-assignment PDF | USD 39.00 (Pine64 store) | |
| PINE A64 / PINE A64+ | Pine64 | SBC | 512 MB, 1 GB or 2 GB DDR3 | GbE (A64+) or 10/100 (512 MB board), HDMI, MIPI DSI, CSI, 2x USB 2.0, Pi-2 and Euler GPIO headers | Schematic PDFs: 512 MB Rev B, A64+ 1 GB Rev B, A64+ 2 GB Rev C (2016-01-13), Wi-Fi/BT module; connector pin assignment | ||
| SOPINE Model A Baseboard | Pine64 | Carrier | OrCAD schematic DSN and PDF (Rev B, 2017-02-07), PCB job archive, Gerbers, layout PDF | ||||
| Clusterboard | Pine64 | Carrier, Mini-ITX, 167 x 170 mm | 8-port GbE switch (RTL8370N), 7x RTL8211E PHYs, 7x USB 2.0, ATX or 5 V barrel power | Schematic DSN and PDF (v2.2), PCB .brd, Gerbers, layout PDF | USD 99.99 (Pine64 store, out of stock) | ||
| PinePhone | Pine64 | Dev kit, Phone, 160.5 x 76.6 x 9.2 mm | 3 GB LPDDR3 (Beta Edition with Convergence Package) | 32 GB eMMC, LTE modem, GPS, USB-C with DisplayPort Alt Mode, Hardware privacy switches | Mainboard schematic PDFs v1.1, v1.2, v1.2a, v1.2b; v1.1 placement PDFs; USB-C board schematic and placement | USD 199.99 (Pine64 store) | |
| PineTab | Pine64 | Dev kit, Tablet, 10.1 in 1280x800 | 2 GB LPDDR3 | 64 GB eMMC, Mini HDMI, USB 2.0 OTG and host, 2 MP front, 5 MP rear camera | Mainboard schematic PDF v1.2 (2019-11-25), top and bottom placement PDFs, keyboard schematic | ||
| Pinebook (11.6 in and 14 in) | Pine64 | Dev kit, Laptop, 11.6 in or 14 in | 2 GB | 16 GB eMMC module, microSD, Optional USB 10/100 Ethernet dongle | Mainboard schematic PDF v3.0, daughter-board schematic PDF | ||
| NanoPi A64 | FriendlyELEC | SBC, 64 x 60 mm, 6-layer | 1 GB DDR3 | GbE (RTL8211E), 2x USB 2.0 host, MIPI DSI, DVP camera, AXP803 PMIC, 40-pin GPIO | Schematic PDF (1610) and DXF dimensions | ||
| Banana Pi BPI-M64 | Banana Pi (Sinovoip) | SBC | |||||
| Orange Pi Win / Win Plus | Shenzhen Xunlong (Orange Pi) | SBC, 93 x 60 mm | 1 GB (Win) or 2 GB (Win Plus) DDR3L | GbE (RTL8211E), 4x USB 2.0 via hub, OTG, HDMI, Wi-Fi, BT (AP6212) |
Prices and links as checked on the dates in our data; the latest check on this page was 2026-10-13. Amazon links marked * are affiliate links; see our disclosure.
Boards with published design files
| Project | Author | Files | Tool | License |
|---|---|---|---|---|
| A64-OLinuXino (Rev H, plus Rev A and B sources) | Olimex | KiCad schematic (.sch, hierarchical) and PCB (.kicad_pcb), Netlist and symbol libraries, Gerbers and drill files, 6 copper layers (Rev H), BOMs for six variants (CSV, ODS, PDF), Schematic PDF, STEP and WRL 3D models | KiCad | OSHWA certified (UID BG000042); OSHWA lists hardware license as Other, documentation CC BY-SA; no license file in the repository |
| TERES-I laptop: TERES-PCB1-A64-MAIN and peripheral boards | Olimex | KiCad schematic and PCB for the A64 main board Rev.B and Rev.C, Gerbers and drill (main board Rev.B), BOM and component lists (Rev.B), Schematic PDF (Rev.C), KiCad sources for IO, touch-button and other boards | KiCad | Repository license file: Apache-2.0 |
| SOPINE Model A Baseboard (Rev B, 2017-02-07) | Pine64 | OrCAD schematic DSN, Schematic PDF, PCB job archive (tar), Gerbers (tar), PCB layout PDF (tar) | OrCAD | None stated; Pine64 calls it open source but "not OSH compliant" |
| Pine64 Clusterboard v2.2 | Pine64 | Schematic capture DSN, Schematic PDF, PCB .brd, Gerbers (RAR), PCB layout PDF | OrCAD | None stated |
Buying the chip
LCSC stocks the A64-H in small quantities; no A64 listing was found at Mouser or DigiKey. Allwinner does not publish a distributor list we could confirm. Pine64 states the R18 has a 10-year supply commitment from Allwinner and lists A64-LTS supply until at least 2025 and SOPINE until at least March 2025; both were still in stock on 2026-10-13.
- LCSC (A64-H)
- Listed as A64-H, part C3036453, BGA-396, Allwinner Tech; USD 13.58 at 1, 12.15 at 10, 10.92 at 30, 10.19 at 119 (one tray); 8 in stock on 2026-10-13. No datasheet attached to the listing. The LCSC photo shows the package marked A64-H.
- Olimex
- A64 in stock at EUR 10.25; minimum standard packing is a tray of 119, factory standard packing 1190 (vacuum sealed).
- Olimex (AXP803)
- AXP803 PMIC, EUR 5.00, in stock.
Datasheet, TRM and design documents
Linked where they are publicly hosted; we do not rehost Allwinner documents. These are third-party documents: we are not responsible for their accuracy, availability or confidentiality status. Disclosure.
- DatasheetAllwinner A64 Datasheet (Pine64 labels it A64/R18)V1.1 · 2015-06-26 · hosted by Pine64 · checked 2026-10-13
- DatasheetAllwinner A64 Datasheet (same file, FriendlyELEC copy)V1.1 · 2015-06-26 · hosted by FriendlyELEC · checked 2026-10-13
- TRMAllwinner A64 User ManualV1.1 · 2015-06-25 · hosted by FriendlyELEC · checked 2026-10-13
- TRMAllwinner A64 User ManualV1.0 · 2015-03-30 · hosted by Pine64 · checked 2026-10-13
- Product briefAllwinner A64 briefv1.0 · 2015-03-23 · hosted by Pine64 · checked 2026-10-13
- Product briefAllwinner R18 brief sheet2015 · hosted by Pine64 · checked 2026-10-13
- PMICX-Powers AXP803 DatasheetRev 1.0 · 2015-04-27 · hosted by Pine64 · checked 2026-10-13
- OtherPINE A64-LTS SoC and memory specification (R18 and A64 identical, 1152 MHz)hosted by Pine64 · checked 2026-10-13
- OtherPINE A64-LTS datasheets page (A64/R18 documents, AXP803, LPDDR3, eMMC)hosted by Pine64 · checked 2026-10-13
- Board schematicOlimex A64-OLinuXino Rev H schematic (A64 + AXP803 + DDR3L)Rev H · hosted by Olimex (GitHub) · checked 2026-10-13
- OtherOlimex A64-OLinuXino hardware sources and revision loghosted by Olimex (GitHub) · checked 2026-10-13
- Board schematicPINE A64+ 2GB schematicRev C · 2016-01-13 · hosted by Pine64 · checked 2026-10-13
- Board schematicPINE A64-LTS schematic (LPDDR3)2018-01-30 · hosted by Pine64 · checked 2026-10-13
- Board schematicSOPINE A64 module schematicver 0.9 · hosted by Pine64 · checked 2026-10-13
- Board schematicPinePhone mainboard schematic (A64 + AXP803 + LPDDR3)v1.2b · hosted by Pine64 · checked 2026-10-13
- Board schematicFriendlyELEC NanoPi A64 schematic1610 · hosted by FriendlyELEC · checked 2026-10-13
- OtherLinux sun50i-a64-cpu-opp.dtsi (CPU OPP table to 1152 MHz)hosted by kernel.org · checked 2026-10-13
- OtherLinux commit: add Jide Remix Mini PC (H64, "a relabelled A64")2024-02-09 · hosted by kernel.org · checked 2026-10-13
- Otherlinux-sunxi A64 page (datasheet, user manual V1.1, AXP803, brief and multimedia list mirrored)community mirror (linux-sunxi), not hosted by Allwinner · checked 2026-10-13
Questions about the A64
Not the A64 itself. We have designed and brought up boards on the Allwinner T507 and A527/T527, and on the Rockchip RV1106, RV1126, RV1126B, RK3566, RK3568, RK3576 and RK3588. The work carries over: power tree, DDR and high-speed layout, bring-up and the BSP, read against this chip's own datasheet.
The newest datasheet is V1.1 (2015-06-26), hosted by Pine64, FriendlyELEC and Olimex on GitHub. The user manual (register-level reference) is V1.1 (2015-06-25) on FriendlyELEC and V1.0 (2015-03-30) on Pine64 and Olimex. The AXP803 PMIC datasheet Rev 1.0 is on Pine64. linux-sunxi mirrors all of them on its A64 page.
None that any public document shows. The R18 brief lists the same CPU, GPU, video, display, interfaces and BGA396 package as the A64; Pine64 says they are identical and that the R18 carries a 10-year supply commitment. The H64 is the OTT-box name: the mainline kernel describes it as a relabelled A64 and boots it with the A64 device tree, and TF-A builds one platform for A64, H5 and H64.
Among the most complete of any low-cost SoC: CPU, DVFS to 1152 MHz, MMC, USB, Ethernet, HDMI, LVDS, MIPI DSI, Lima GPU, Cedrus decode (MPEG-2, H.264, H.265, VP8), parallel CSI, audio, crypto and thermal are upstream between 4.10 and 5.7, with 19 board device trees. Mainline U-Boot has open DRAM init, TF-A and crust are upstream, so no binary blobs are needed to boot. Missing: a mainline hardware encoder.
Yes. Olimex publishes the complete KiCad project for A64-OLinuXino (schematic, 6-layer PCB, Gerbers, BOMs, 3D models; OSHWA certified BG000042) and for the TERES-I laptop main board. Pine64 publishes OrCAD schematics, PCB job files and Gerbers for the SOPINE Model A Baseboard and the Clusterboard, and schematic PDFs for PINE A64, A64-LTS, SOPINE, Pinebook, PinePhone and PineTab.
No. Its high-speed interfaces are DDR3/LPDDR3, one RGMII GbE MAC, HDMI 1.4, 4-lane MIPI DSI and two USB 2.0 ports. Cameras connect over an 8-bit parallel CSI bus (5 MP stills, 1080p30 video). For PCIe or USB 3.0 look at the H6 or RK3328 class.
Every public A64 design checked uses the X-Powers AXP803, which supplies the CPU (DCDC2 and DCDC3 dual-phase), DRAM, system and I/O rails and includes a Li-ion charger. For a module, Pine64 SOPINE (2 GB LPDDR3, DDR3 SO-DIMM edge, USD 32.99) is the one still sold; its schematic and the open SOPINE baseboard sources are published.
Related chips and reading
- H618 / H616Pi Zero class SBCs, CM4-style 3D-printer SoMs, TV boxes, retro handhelds (H700)
- A133 / R818Tablets, HMI panels, smart displays, handhelds
- H64K TV boxes, media players, low-cost Linux SBCs with USB 3.0
- RK3328Routers, TV boxes, Klipper hosts
- RK3326 / PX30Handhelds, HMI panels, smart audio, kiosks
- RK3566HMI, e-ink readers, handhelds, CM4-class SoMs, small routers
- A527 / T527Industrial HMI, dual-display terminals, gateways, robots, tablets
We'll design your A64 board.
Tell us the interfaces, power budget and volume. An engineer replies with questions or a proposal.
Links and facts on this page checked 2026-10-13. Spotted something out of date? Tell us through the contact form.
Compiled from publicly available sources: datasheets, technical reference manuals, vendor product pages, schematics and source code published by their owners and third parties. We link to documents where others host them and do not host, endorse or vouch for them. Everything on these pages, including our own specs, summaries, block diagrams, comparisons, calculators and design notes, is for reference only and may contain errors or be out of date. It is provided as is, and Groundplane is not responsible for errors in it, for third-party documents, or for any design, board or decision based on it. Always check the manufacturer's current datasheet, reference manual and design guidance before you design a board. Rockchip, Allwinner, Raspberry Pi and other product names are trademarks of their owners; we are not affiliated with any of them. See our disclosure.