A133 / R818
Low-cost quad Cortex-A53 SoC for tablets, HMI panels and smart displays: MIPI DSI, dual-link LVDS or RGB up to 1920 x 1200, 4K30 H.265/H.264 decode, one GbE MAC, USB 2.0 only, no PCIe and no HDMI, in a 12 x 12 mm BGA at about USD 4 to 6.
- CPU
- 4x A53 up to 1.6 GHz
- GPU
- PowerVR GE8300
- NPU
- None
- Video
- 4K30 H.265/H.264 dec, 1080p60 H.264 enc
- PCIe
- None
What the A133 / R818 is for
Right for
- Cost-driven Android or Linux HMI panels up to 1920 x 1200: one 4-lane MIPI DSI, dual-link LVDS or parallel RGB from a single 12 x 12 mm package that LCSC sells at USD 4.16 in 100s
- Battery tablets and handhelds: the reference platform pairs it with an X-Powers PMIC that has a single-cell charger (AXP707/AXP803 or AXP717), and the A133P bin powers the TrimUI Smart Pro handheld
- Smart displays and voice terminals: on-chip codec with 2 ADC and 2 DAC, up to 8 PDM microphones, four I2S/TDM ports (R818 is the same die sold as an audio processor)
- Video playback appliances that need 4K30 H.265 or H.264 decode and 1080p60 H.264 encode but only a panel-class output
- Wide-temperature HMI on the R818 ordering code: its datasheet rates -40 to 85 C ambient against -20 to 70 C for the A133
Wrong for
- Anything that needs HDMI, eDP or DisplayPort: the only outputs are MIPI DSI, LVDS, RGB, serial RGB, i8080 and BT.656
- NVMe, PCIe Wi-Fi, SATA or USB 3: there is no SerDes at all, only one USB 2.0 OTG and one USB 2.0 host port
- Products that must ship on mainline Linux with a GUI today: display, GPU, video engine and audio codec have no mainline drivers as of 7.3-rc7
- More than 4 GB of DRAM or DRAM above 792 MHz
- On-device AI: there is no NPU
Cost and constraints
- BOM is the SoC (USD 4.16 at 100 pieces for A133, USD 5.72 for R818 on LCSC), an X-Powers PMIC (AXP803/AXP707 on every mainline board, AXP717 on MangoPi mCore-R818) and 32-bit DDR3, DDR4, LPDDR3 or LPDDR4
- LFBGA346, 12 x 12 mm, 0.5 mm ball pitch, 0.3 mm balls: check via-in-pad and fanout capability with your fab before fixing the stackup
- Software is effectively Allwinner's Tina/Longan BSP (Linux 4.9 trees in the public BSP repos checked) or Android; mainline covers headless use only
- A133 is rated -20 to 70 C ambient; the industrial range exists only on the R818 part number
- No public hardware design guide or layout guide; DDR routing must be copied from a vendor design or obtained from Allwinner under agreement
Inside the A133 / R818
Drawn by Groundplane from the datasheet rev 1.1. Not Allwinner artwork.
- 32-bit DDR3/DDR4/LPDDR3/4
- eMMC 5.1 (8-bit)
- SD 3.0
- 8-bit raw NAND
- SPI NOR or NAND
- 4x Cortex-A53 up to 1.6 GHz
- 32 KB L1 I/D per core
- 512 KB shared L2
- NEON, VFPv4, TrustZone
- PowerVR GE8300
- GLES 3.2, Vulkan 1.1
- G2D rotate and scale
- None
- 4K30 H.265/H.264 decoder
- 1080p60 H.264 encoder
- MJPEG encoder
- 32-bit DRAM controller
- DDR3/DDR4/LPDDR3/LPDDR4
- Up to 4 GB at 792 MHz
- NAND controller, 80-bit ECC
- DE 2.0, SmartColor 2.0
- TCON: RGB or dual-link LVDS
- 4-lane MIPI DSI
- MIPI CSI 4-lane + 2-lane
- ISP 8 MP 30 or 13 MP 10
- Crypto engine, TRNG
- Secure BROM
- 2 Kbit eFuse
- CPUS low-power domain
- IOMMU, 8-ch DMA
- 3 thermal sensors
- Audio codec, DMIC, I2S x4
- USB 2.0 OTG (FEL port)
- USB 2.0 host
- GbE MAC (RGMII/RMII)
- SDIO 3.0 for Wi-Fi
- MIPI DSI x4, LVDS, RGB
- MIPI CSI x4 + x2
- Headphone, line out, 2 mics
- I2S x4, DMIC, S/PDIF out
- UART x6, SPI x3, TWI x6, PWM x5
Read from the documents
Each value names the document it was read from.
| CPU | 4x Cortex-A53, 32 KB L1 I/D each, 512 KB shared L2, NEON, VFPv4, TrustZone; up to 1.6 GHz | Datasheet Rev 1.1, 2.1 |
|---|---|---|
| GPU | Imagination PowerVR GE8300; OpenGL ES 1.1/2.0/3.2, Vulkan 1.1, OpenCL 1.2 | Datasheet Rev 1.1, 2.2 |
| NPU | None (no neural accelerator in the feature list) | Datasheet Rev 1.1, 2 |
| Video decode | H.265 MP@L5.0 and H.264 BP/MP/HP@L5.1 up to 4K at 30 fps; VP9 720p30; MPEG-1/2/4, VP8, AVS/AVS+, H.263, MJPEG 1080p60; VC-1 1080p30 | Datasheet Rev 1.1, 2.4.1 |
| Video encode | H.264 BP/MP/HP up to 1080p60, maximum frame size 4096 x 4096 | Datasheet Rev 1.1, 2.4.2 |
| JPEG | MJPEG encode 1080p30 (datasheet); the product brief lists MJPEG/JPEG baseline encode at 4K15 | Datasheet Rev 1.1, 2.4.2 |
| ISP | One ISP: one sensor online at 8 MP 30 fps or two sensors offline at 13 MP 10 fps; 3A, defect pixel correction, 2D denoise, global tone mapping | Datasheet Rev 1.1, 2.7.2 |
| Memory | 32-bit DDR3, DDR3L, DDR4, LPDDR3, LPDDR4, each at up to 792 MHz clock; 4 GB max | Datasheet Rev 1.1, 2.3.2 |
| Storage | eMMC 5.1 (8-bit, HS200 at 1.8 V), SD 3.0, SDIO 3.0, 8-bit raw NAND (ONFI 2.0, Toggle 2.0, up to 80-bit ECC per 1 KB), SPI NOR and SPI NAND boot | Datasheet Rev 1.1, 2.3.1, 2.3.3, 2.3.4 |
| Display | One TCON_LCD: RGB up to 1920 x 1200 at 60 fps, dual-link LVDS up to 1920 x 1200 at 60 fps (single link 1366 x 768), serial RGB and i8080 up to 800 x 480, BT.656; one 4-lane MIPI DSI 1.01 up to 1920 x 1200 at 60 fps. No HDMI. DE 2.0 with SmartColor 2.0, G2D rotate and scale up to 2048 x 2048 | Datasheet Rev 1.1, 2.5, 2.8 |
| Camera | 2x MIPI CSI-2 (one 4-lane, one 2-lane), MIPI 1.0 at up to 1.0 Gbps per lane; 8 MP 30 fps online, 13 MP 10 fps offline, or 4x 1080p25 through a deinterleaver chip | Datasheet Rev 1.1, 2.7.1 |
| PCIe | None | Datasheet Rev 1.1, 2.11 |
| USB | 1x USB 2.0 OTG (USB0, also the FEL upgrade port) and 1x USB 2.0 host (USB1), both with integrated PHYs. No USB 3 | Datasheet Rev 1.1, 2.11.1 |
| Ethernet | 1x EMAC 10/100/1000, RGMII or RMII, MDIO, jumbo frames up to 16 KB | Datasheet Rev 1.1, 2.11.2 |
| SATA | None | Datasheet Rev 1.1, 2.11 |
| Audio | Codec with 2 DAC (8 to 192 kHz) and 2 ADC (8 to 48 kHz), stereo headphone and differential line out, 2 differential mic inputs with bias; 4x I2S/PCM/TDM (up to 16 channels); DMIC up to 8 microphones; S/PDIF (OWA) TX | Datasheet Rev 1.1, 2.9 |
| Security | Crypto engine (AES, XTS-AES, DES/TDES, SM4, MD5, SHA-1/2, SM3, HMAC, RSA to 4096, ECC to 521, TRNG); 2 Kbit eFuse; secure BROM loads only certified firmware | Datasheet Rev 1.1, 2.3.1, 2.10 |
| Other I/O | 6x UART (incl. S_UART), 3x SPI (quad), 6x TWI, 5x PWM, 1-channel 12-bit GPADC, 1-channel 6-bit LRADC, LEDC for up to 1024 serial LEDs, CIR TX and RX; 243 I/O balls | Datasheet Rev 1.1, 2.11, Table 4-1 |
| Package | LFBGA346, 12 x 12 mm, 0.5 mm ball pitch, 0.3 mm balls; MSL3; 168 per tray | Datasheet Rev 1.1, 2.12, 8.1, 8.2.1 |
| Temperature | A133: ambient -20 to 70 C, Tj -20 to 110 C recommended, Tj absolute max 125 C. R818: ambient -40 to 85 C, Tj -40 to 110 C | Datasheet Rev 1.1, Table 5-1, Table 5-2; R818 Table 5-2 |
| Thermal | theta-JA 23.45, theta-JB 6.46, theta-JC 3.01 C/W (JEDEC JESD51); three on-die sensors (CPU, GPU, DDR), accuracy 3 C from 0 to 100 C | Datasheet Rev 1.1, Table 6-1, 2.6.7 |
Variants
| A133 | Base tablet part: quad A53 at up to 1.6 GHz in the datasheet (the product brief and LCSC say 1.5 GHz), ambient -20 to 70 C, LFBGA346. | Datasheet Rev 1.1 |
|---|---|---|
| R818 | Same feature list, package, pinout tables and thermal resistance as the A133, sold as an "audio application processor" for smart displays. The datasheet gives no CPU clock and rates ambient -40 to 85 C and Tj -40 to 110 C. linux-sunxi lists the Creality T800 in the Sonic Pad as a rebadged R818. | Datasheet Rev 1.5 |
| A133P (A133 Plus) | Higher CPU speed bin, reported by linux-sunxi at up to 2.0 GHz from vendor OPP tables that read an eFuse bin field; used in the TrimUI Smart Pro. No Allwinner document for A133P was found. | Other |
| A100 | Lowest bin of the same die (sun50iw10). There has never been a public A100 datasheet; mainline Linux uses the sun50i-a100 compatible for all of these parts, and its CPU OPP table stops at 1.464 GHz. | Other |
What to watch when you design with it
Power and PMIC
Allwinner's brief names a customized AXP707 for the A133, and linux-sunxi lists AXP707 as another name for the AXP803 (6 bucks, 15 LDOs, single-cell charger). Every A133 board with a mainline device tree (Liontron H-A133L, Baijie Helper A133, Allwinner A100 Perf1) describes an AXP803 on the R_TWI bus; the Liontron BSP boot log also reports "PMU: AXP803". Its mainline DT is a usable rail map: DCDC2 0.81 to 1.2 V for VDD_CPU, DCDC3 0.9 V for VDD_CPUS/VDD_USB, DCDC4 0.95 V for VDD_SYS, DCDC5 1.1 V for LPDDR4 VCC_DRAM, ALDO2 1.8 V for VDD18_DRAM, ALDO1 1.8 V for the codec AVCC, DCDC1 3.3 V for VCC_IO and eMMC, ELDO1 1.8 V for the eMMC I/O bank. MangoPi's mCore-R818 uses an AXP717 instead. Datasheet sequencing: VCC_RTC first; VDD_SYS, VDD18_DRAM, AVCC and VCC_PLL at least 8 ms after it; VCC_EFUSE after VDD_SYS; release RESET at least 6 ms after the rails settle.
Sources: Datasheet Rev 1.1, Product brief, PMIC Rev 1.0, Other, linux-sunxi.org, linux-sunxi.org, Board schematic V3 and V3p1
DDR
One 32-bit channel, 4 GB maximum, every DRAM type capped at a 792 MHz clock in the datasheet. VCC_DRAM is 1.2 V for DDR4 and LPDDR3, 1.1 V for LPDDR4, 1.5 V for DDR3 and 1.35 V for DDR3L, plus a separate 1.8 V VDD18_DRAM pad supply. Public boards checked use LPDDR4 (Liontron, Baijie, MangoPi, TrimUI) or DDR3 (Kickpi K5C per linux-sunxi). linux-sunxi documents the controller as a Synopsys uMCTL2 with a PHY similar to the H616. Mainline U-Boot has had an open A133 DRAM init driver since v2025.10, so a blob-free boot chain is possible. No Allwinner DDR layout guide is linkable; copy a vendor layout such as the MangoPi R818-IOBoard or the A-Pocket core board.
Sources: Datasheet Rev 1.1, linux-sunxi.org, github.com
High-speed interfaces
There is no SerDes: the fastest external links are the 4-lane MIPI DSI, the 4-lane plus 2-lane MIPI CSI (1.0 Gbps per lane), dual-link LVDS, USB 2.0 and the RGMII EMAC. Wi-Fi goes on SDIO 3.0 (the brief pairs XR829 or AW859A; Kickpi and Baijie use AW869A, which has no mainline driver). A second network port or a modem has to come from USB 2.0: Kickpi offers a Quectel EC20 or EC200 4G module on the K5C, and with no PCIe on the SoC that modem can only be on USB. LVDS has its own 1.8 V VCC_LVDS rail and MIPI CSI its own 1.8 V VCC_MCSI.
Sources: Datasheet Rev 1.1, Product brief, kickpi.com, lkml.indiana.edu
Boot and FEL
The BROM boots from SD (SMHC0), eMMC (SMHC2), raw NAND, SPI NOR or SPI NAND and always tries the SD slot first. The boot-select method is set by the BOOT_MODE eFuse bits: unfused parts use GPADC select, where the voltage on the BOOT_SEL_ADC ball picks the order (for example eMMC user area, or SPI NOR, after SD), so the resistor divider on that ball is a schematic decision. GPIO pin select and eFuse select are the other modes. If the FEL ball is low at reset the BROM enters USB FEL upgrade mode on the USB0 OTG port; boards expose this as a FEL button (Liontron, Kickpi, MangoPi carrier). Secure boot checks X.509-signed firmware with RSA-2048 and SHA-256.
Sources: TRM Rev 1.1, Datasheet Rev 1.1, linux-sunxi.org, kickpi.com
Thermal
Datasheet thermal resistance is theta-JA 23.45 C/W, theta-JB 6.46 C/W and theta-JC 3.01 C/W (JEDEC JESD51), with a recommended Tj ceiling of 110 C. Three on-die sensors sit at the CPU, GPU and DDR controller, and the THS driver has been in mainline since 5.10. Kickpi fits a cooling fan on the K5C; the Creality Sonic Pad (R818) uses a heatsink with thermal pads per linux-sunxi.
Sources: Datasheet Rev 1.1, kickpi.com, linux-sunxi.org
Gotchas
Clock figures disagree: the datasheet says 1.6 GHz, the product brief, LCSC, Kickpi and MangoPi say 1.5 GHz, and mainline only programs up to 1.464 GHz because its OPP table is the A100 bin. No HDMI exists on any variant, so HDMI on a carrier needs an external DSI or RGB bridge. GPIO drive is 6 mA maximum per pin. The R818 is the part to order for -40 to 85 C; an A133 is rated -20 to 70 C. Several vendor pages are inaccurate (Liontron's H-A133 page calls the cores Cortex-A55), so check the SoC marking on any board you copy.
Sources: Datasheet Rev 1.1, Product brief, Datasheet Rev 1.5, Other, en.liontron.cn
Layout guides for the A133 / R818's interfaces
Public layout guidance for each interface this chip has, from vendors who publish it, plus our calculators.
LPDDR4
Point-to-point routing; TI notes that on-die termination on both ends means no board termination is needed. Byte lanes length-matched to their strobe and command/address matched to the clock, all over a solid reference plane. Impedance targets differ by vendor: TI AM62x and ADI EE-480 use 40 ohm single-ended and 80 ohm differential, Synaptics SL1680 uses 50 and 85 ohm, AMD Versal 45 and 82 ohm. Use the SoC vendor's own target and simulate.
- AM62x, AM62Lx DDR Board Design and Layout GuidelinesTexas Instruments, SPRAD06, C, 2025
- AM62Ax, AM62Px, AM62Dx LPDDR4 Board Design and Layout GuidelinesTexas Instruments, SPRAD66, B, 2024
- ADSP-2184x/ADSP-SC84x LPDDR4 Board Design GuidelinesAnalog Devices, EE-480, 1, 2026
- SL1680 General PCB Design and LPDDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001390-01, E
- DDR length matching calculatorGroundplane calculator
DDR4
DDR4 uses pseudo open-drain data signaling and needs a VPP supply, with command/address routed fly-by or as a balanced tree depending on device count. TI AM62x uses 40 ohm single-ended and 80 ohm differential; AMD Versal uses 50 and 90 ohm, relaxed under the BGA. Match data to strobe per byte and command/address to clock.
- AM62x, AM62Lx DDR Board Design and Layout GuidelinesTexas Instruments, SPRAD06, C, 2025
- Versal Adaptive SoC PCB Design User Guide: PCB Routing Guidelines for DDR4 InterfacesAMD, UG863, 1.12, 2026
- SL1640 General PCB Design and DDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001529-01, D
- PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex 5 FPGAs and SoCsAltera, 821801, 2026
- DDR length matching calculatorGroundplane calculator
- Via current calculatorGroundplane calculator
DDR3 / DDR3L
Fly-by command/address with termination at the end of the chain, point-to-point data lanes matched to their strobe, and a clean VREF. ST recommends 55 ohm single-ended and 100 ohm differential for DDR3 and DDR3L on STM32MP1 boards, and shows that a 4-layer board is possible with strict layer allocation.
- STM32MP1 Series DDR memory routing guidelinesSTMicroelectronics, AN5122, 3, 2019
- DDR3 Design Requirements for KeyStone DevicesTexas Instruments, SPRABI1, D, 2022
- SL2610 General PCB Design and DDR3L/DDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001629-01, A, 2025
- DDR length matching calculatorGroundplane calculator
LPDDR3
Point-to-point and normally unterminated, with command/address matched to the clock and each byte matched to its strobe. ST gives the same targets for LPDDR3 as for DDR3: 55 ohm single-ended and 100 ohm differential. Few current public guides cover LPDDR3, so treat the SoC vendor's reference layout as the stronger source.
- STM32MP1 Series DDR memory routing guidelinesSTMicroelectronics, AN5122, 3, 2019
- DDR length matching calculatorGroundplane calculator
eMMC
A single-ended bus: CLK, CMD, DAT0 to DAT7 and, for HS400, the data strobe. TI and Synaptics both route it at 50 ohm single-ended, match the group, and keep stubs short; Synaptics places a 22 or 33 ohm series resistor on CLK and STRB. At HS400 TI also checks the eMMC I/O supply impedance, not just the traces.
- AM62Px eMMC HS400 Board Design and Simulation GuidelinesTexas Instruments, SPRADP5, A, 2026
- Astra Machina Foundation Series eMMC ConfigurationSynaptics, PN 506-001594-01, D
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
SD card / SDIO
Single-ended CLK, CMD and four data lines over a solid ground plane, at constant trace width and matched length. NXP asks for clock-to-neighbor spacing greater than twice the trace height above the plane and 1.5 times for data and CMD, with 45 degree bends. UHS modes switch the I/O to 1.8 V, so a level translator often sits next to the socket.
- NVT4557/NVT4558/NVT4858 voltage-level translator layout guidelineNXP, AN13158, 1.1, 2022
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
- SD Physical Layer Simplified SpecificationSD Association, 9.10, 2023
PCIe
AC-coupled differential lanes routed with no stubs, minimal vias and back-drilled or blind vias where speed demands, with lane-to-lane skew handled by the receiver. Targets differ by guide: TI Jacinto 7 uses 85 ohm differential for lanes and 100 ohm for the reference clock, while TI's earlier SoC guide tabulates 100 ohm and, for some devices, 95 ohm. Match the target to your connector and stackup.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
USB 3.x
SuperSpeed TX and RX pairs are routed at 90 ohm differential in all three TI guides (SPRAAR7 lists 95 ohm for some devices), with AC coupling capacitors on TX, symmetric pad and via placement, and matched via counts within each pair. Keep the pairs away from the USB 2.0 pair and other aggressors, and place ESD at the connector.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
USB 2.0
One D+/D- pair at 90 ohm differential, routed in parallel for its whole length with minimal deviations at the connector and package. NXP keeps clocks and periodic signals at least 50 mils away and other signals at least 20 mils away from the pair.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
HDMI
Four TMDS pairs (three data, one clock) at 100 ohm differential, as both TI guides state, with tight intra-pair matching and as few vias as possible between the SoC and the connector. HDMI also needs 5 V supply switching, DDC and CEC level handling, hot-plug detect and ESD at the connector.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- TPD12S016 PCB Layout Guidelines for HDMI ESDTexas Instruments, SLLA324, 2012
MIPI DSI
MIPI D-PHY clock and data lanes are routed as 100 ohm differential pairs over a solid reference; TI Jacinto 7 allows no stubs, 2 vias per trace and 40 ps lane-to-lane skew. Connectors and flex cables to the panel are usually the largest discontinuity, so keep the board segment short and clean.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex 5 FPGAs and SoCsAltera, 821801, 2026
MIPI CSI-2
Same D-PHY rules as DSI: 100 ohm differential lanes in both TI guides, with lane-to-lane skew bounded (40 ps in TI Jacinto 7). Size the lane count and lane rate from the sensor's output format before routing.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex 5 FPGAs and SoCsAltera, 821801, 2026
- MIPI CSI-2 bandwidth calculatorGroundplane calculator
LVDS
Tightly coupled differential pairs terminated at the receiver in 100 ohm, with TI's EMI guide asking for 100 ohm differential traces within 5 percent. Keep pairs matched and away from other aggressors, and avoid stubs and reference plane gaps along the route to the panel connector.
- LVDS Owner's Manual: Including High-Speed CML and Signal ConditioningTexas Instruments, SNLA187, 4th edition, 2008
- High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes DesignsTexas Instruments, SNLA302, 2018
- LVDS SerDes Gen I PCB and Interconnect Design-In GuidelinesTexas Instruments, SNLA008, A, 2018
Ethernet (RGMII / RMII)
TI routes MAC-to-PHY (MII family) traces at 50 ohm single-ended, under 6 inches, matched within 20 mils for gigabit, and the PHY-side MDI pairs at 100 ohm differential. RGMII also needs a 1.5 to 2.0 ns clock-to-data delay, added on the board or inside the MAC or PHY (RGMII-ID); decide which before layout so it is not applied twice.
- Ethernet PHY PCB Design Layout ChecklistTexas Instruments, SNLA387, 2021
- PCB Design Guideline for RGMII InterfaceRenesas, R01AN6272EJ0141, 1.41, 2026
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
SATA
AC-coupled TX and RX pairs at 100 ohm differential in TI's SoC guide, routed with the same via, stub and reference plane rules as PCIe and USB 3. On Rockchip parts SATA usually shares a combo PHY with PCIe or USB 3, so the lane is routed once to whichever connector the design picks.
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
Board-level design guides
Impedance and timing, power, thermal and ESD guidance that applies to any board around this chip.
Impedance and timing
Every high-speed interface on the board comes down to the same two numbers: the trace impedance your stackup actually gives, and the delay each trace adds. Set the stackup with your fab first, then route to its impedance table and match lengths in time, not millimeters, where the layers differ.
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- PCB impedance calculatorGroundplane calculator
- PCB propagation delay calculatorGroundplane calculator
Power delivery
For each switching regulator, place and route the input capacitor first, keep the switching current loop small, and keep the switch node short. Give the SoC rails solid planes and decoupling at the balls, and size current-carrying copper and vias for the real load.
- Five steps to a great PCB layout for a step-down converterTexas Instruments, SLYT614, 2015
- AN-1149 Layout Guidelines for Switching Power SuppliesTexas Instruments, SNVA021, C, 2013
- AN-1229 SIMPLE SWITCHER PCB Layout GuidelinesTexas Instruments, SNVA054, C, 2013
- Buck converter calculatorGroundplane calculator
- LDO power dissipation calculatorGroundplane calculator
- PCB trace width calculatorGroundplane calculator
- Via current calculatorGroundplane calculator
Thermal
Theta-JA is measured on a JEDEC test board that carries most of the heat, so it does not transfer directly to a product board; use it to compare packages and use the psi metrics for estimates. Thermal vias under the package, copper area and copper thickness move the most heat into the board.
- Semiconductor and IC Package Thermal MetricsTexas Instruments, SPRA953, D, 2024
- AN-2020 Thermal Design By Insight, Not HindsightTexas Instruments, SNVA419, C, 2013
- Heatsink thermal resistance calculatorGroundplane calculator
- LDO power dissipation calculatorGroundplane calculator
ESD protection
Place the TVS as close to the connector as design rules allow, route from the connector to the TVS with no stub, and keep the protected IC further from the TVS than the TVS is from the connector. Choose parts by clamping performance and by capacitance low enough for the interface speed.
- ESD Protection Layout GuideTexas Instruments, SLVA680, A, 2022
- Reading and Understanding an ESD Protection Data SheetTexas Instruments, SLLA305, A
- TPD12S016 PCB Layout Guidelines for HDMI ESDTexas Instruments, SLLA324, 2012
- PCB conductor spacing calculator (IPC-2221)Groundplane calculator
Allwinner's hardware design guide
Allwinner's hardware design guide, EVB reference schematics and DDR templates come from Allwinner or an authorized agent, usually under NDA, or through your SoM vendor. We do not link copies circulating elsewhere. The vendor schematics and open designs on the Boards tab are real, shipped layouts on the A133 / R818 and the best public reference.
BSP, mainline and toolkits
| Area | Status | Links |
|---|---|---|
| Vendor BSP kernel | Allwinner ships Tina Linux / Longan SDKs and Android to customers. The public BSP trees checked carry Linux 4.9: Creality's Sonic Pad OS (R818) has lichee/linux-4.9, and 100ask's DshanPI-ROSx Tina SDK patches target lichee/linux-4.9. 100ask documents Tina SDK V2.5, Tina 5 and Android 13 for its A133 board.Checked 2026-10-13 | |
| Mainline Linux | Headless support only. SoC dtsi, CCU, pin controller and thermal sensor landed in 5.10 (sun50i-a100 compatible, used for A133 and R818 too); USB, MMC, watchdog and PMU nodes in 6.13; LVDS pin functions in 6.14; CPU OPP table (to 1.464 GHz) in 6.15; Liontron H-A133L, the first A133 board, in 6.16; EMAC in 6.17; LED controller in 7.0; LRADC and the Baijie Helper A133 board queued for 7.3 (present in 7.3-rc7). Not upstream as of 7.3-rc7: display engine, TCON and MIPI DSI, GPU (the PowerVR binding has no GE8300 entry), video engine (no Cedrus compatible), audio codec, CSI and ISP.Checked 2026-10-13 | |
| U-Boot | Mainline U-Boot added A133 DRAM init (dram_sun50i_a133.c) and the Liontron H-A133L target (liontron-h-a133l_defconfig) in v2025.10; it is still the only A133 defconfig in v2026.10. Vendor builds use Allwinner's boot0 plus a U-Boot 2018 fork (brandy-2.0).Checked 2026-10-13 | |
| TF-A | A plat/allwinner/sun50i_a133 port was merged to TF-A master on 2026-06-11, after the v2.15.0 release, so it is not in a tagged release yet. Vendor SDKs ship a prebuilt bl31.bin.Checked 2026-10-13 | |
| GPU and video | PowerVR GE8300 runs only on Allwinner's BSP with Imagination's closed driver. Video decode and encode use Allwinner's CedarX/libcedarc userspace on the BSP kernel; a community port of libcedarc for A133 with glibc exists. Nothing in mainline as of 7.3-rc7.Checked 2026-10-13 | |
| Android | Allwinner's brief lists Android 10 and above. Kickpi ships Android 10 and Ubuntu 16.04 for the K5C; 100ask lists Android 13; Liontron ships Android on the H-A133L.Checked 2026-10-13 | |
| Distributions | No Armbian, Buildroot or OpenWrt board configs for A133 boards. Community images exist for consumer devices: a Debian port for the Creality Sonic Pad (R818) and a mainline Linux and U-Boot port for the TrimUI Smart Pro (A133P) that boots to a shell but has no working display yet.Checked 2026-10-13 | |
| Community | linux-sunxi wiki (A133 page, DRAM controller notes, device pages with FEL and UART instructions); 100ask forum for the DshanPI board.Checked 2026-10-13 |
A133 / R818 system on modules
Any of these can sit on a carrier board we design.
| Module | Vendor | Connector | RAM | Design files | Buy |
|---|---|---|---|---|---|
| mCore-R818 | MangoPi | Solder-down module, 32 x 32 x 3 mm | 1, 2 or 4 GB LPDDR4 | Module schematic PDFs (V3, V3p1); reference carrier R818-IOBoard as Altium project and Gerbers | |
| A133 Core | Baijie | Castellated (stamp hole) per the A-Pocket project | 1, 2 or 4 GB LPDDR4 (8 to 32 GB eMMC) | None found; mainline Linux DT (sun50i-a133-helperboard-core.dtsi) queued for 7.3 |
Every public A133 / R818 board
| Board | Vendor | Type | RAM | Notable I/O | Design files | Buy |
|---|---|---|---|---|---|---|
| H-A133L | Liontron | SBC, 100 x 80 mm | Up to 4 GB (LPDDR4 per linux-sunxi) | LVDS or MIPI DSI, 10/100 Ethernet, PoE input, Up to 5 USB 2.0, Up to 2 RS232, 1 as RS485, 9 to 15 V input | Specification and mechanical drawing PDFs; mainline Linux DT since 6.16 and U-Boot since v2025.10 | |
| H-A133 | Liontron | SBC, 100 x 80 mm | Up to 2 GB | MIPI or LVDS, RGB, 10/100 Ethernet, 2 external and 5 internal USB 2.0, 2 TTL/RS232, 1 TTL/RS485 | Specification and mechanical drawing PDFs | |
| H-A133R | Liontron | SBC, 100 x 80 mm | Up to 4 GB | 40-pin or 50-pin RGB panel, 10/100 Ethernet, PoE, Up to 5 USB 2.0, RS232/RS485 | Specification and mechanical drawing PDFs | |
| K5C | Kickpi | SBC | 2 GB (8 GB eMMC) | GbE, MIPI DSI, dual-link LVDS, 2x USB 2.0 host, Wi-Fi and BT (AW869A), 4G module socket, 20-pin expansion | "Hardware" download folder on OneDrive; contents not checked | |
| Helper A133 board | Baijie | Dev kit | GbE, USB-C OTG via hub, 2x USB 2.0, microSD, LRADC buttons | None found; mainline Linux DT queued for 7.3 | ||
| A133-mCore board (DshanPI-ROSx) | 100ask | Dev kit | Core board in 1 GB + 8 GB or 2 GB + 16 GB | GbE, Wi-Fi 6 and BT, MIPI DSI with touch, MIPI CSI (OV8858), USB-C combined with debug UART, Dual microphones | None found (SDK patches and docs on GitHub) | |
| A133 7-inch HMI board (RWA030) | HYY Technology (we-signage) | SBC, 186.3 x 105.4 mm | 7-inch LCD (AN0708) | PCB outline and top-view DXF and PDF |
Prices and links as checked on the dates in our data; the latest check on this page was 2026-10-13. Amazon links marked * are affiliate links; see our disclosure.
Boards with published design files
| Project | Author | Files | Tool | License |
|---|---|---|---|---|
| MangoPi R818-IOBoard (reference carrier for mCore-R818) | MangoPi | Altium schematics (mCORE, Periph, WIFI-BT), Altium PcbDoc and project, Gerbers and drill, Module schematic PDFs V3 and V3p1 | Altium | None stated |
| A-Pocket A133CoreDK and LCD deck | Forairaaaaa | KiCad schematic and PCB (core carrier and LCD deck), Gerbers and drill, Interactive BOM (HTML) | KiCad | None stated in the repository |
Buying the chip
The datasheet lists trays of 168 and full cartons of 10080. No public listing for the A133P bin or the AXP707 with stock was found; LCSC lists the AXP707 (C2913551, QFN-68 8 x 8 mm) as out of stock. Module vendors (MangoPi, Baijie, 100ask) sell modules, not bare chips.
- LCSC: A133
- C2997892, LFBGA-346; 116 in stock; USD 4.62 at 1, 4.40 at 10, 4.27 at 30, 4.16 at 100.
- LCSC: R818
- C5720369, LFBGA-346 (12 x 12); 351 in stock; USD 6.32 at 1, 6.04 at 10, 5.86 at 30, 5.72 at 100; tray of 168.
- Allwinner direct
- The brief gives service@allwinnertech.com as the sales contact. Allwinner does not publish a distributor list we could confirm.
Datasheet, TRM and design documents
Linked where they are publicly hosted; we do not rehost Allwinner documents. These are third-party documents: we are not responsible for their accuracy, availability or confidentiality status. Disclosure.
- DatasheetAllwinner A133 DatasheetRev 1.1 · 2020-07-14 · hosted by HYY Technology (board vendor, GitHub) · checked 2026-10-13
- TRMAllwinner A133 User ManualRev 1.1 · 2020-07-14 · community mirror (linux-sunxi), not hosted by Allwinner · checked 2026-10-13
- DatasheetAllwinner R818 DatasheetRev 1.5 · 2020-08-12 · hosted by LCSC · checked 2026-10-13
- Product briefAllwinner A133 Product Brief2021 · hosted by LCSC · checked 2026-10-13
- PMICX-Powers AXP803 Datasheet (AXP707 is listed as the same PMIC by linux-sunxi)Rev 1.0 · 2015-04-27 · hosted by Pine64 · checked 2026-10-13
- Board schematicMangoPi mCore-R818 module schematics (R818 + LPDDR4 + AXP717)V3 and V3p1 · hosted by MangoPi · checked 2026-10-13
- Otherlinux-sunxi A133 page (variants, bins, devices)hosted by linux-sunxi · checked 2026-10-13
- OtherLinux commit: add A100 CPU OPP table (up to 1.464 GHz)2025-02-22 · hosted by kernel.org · checked 2026-10-13
- OtherLinux commit: add Liontron H-A133L board support2025-05-14 · hosted by kernel.org · checked 2026-10-13
- OtherAndre Przywara, "Re: A133 support" (A133 as the better bin of the A100; no public A100 manual)2024-10-20 · hosted by LKML archive (iu.edu) · checked 2026-10-13
Questions about the A133 / R818
Not the A133 / R818 itself. We have designed and brought up boards on the Allwinner T507 and A527/T527, and on the Rockchip RV1106, RV1126, RV1126B, RK3566, RK3568, RK3576 and RK3588. The work carries over: power tree, DDR and high-speed layout, bring-up and the BSP, read against this chip's own datasheet.
The board vendor HYY Technology publishes the A133 Datasheet Rev 1.1 (2020-07-14) on GitHub with its 7-inch HMI board files; the User Manual Rev 1.1 is mirrored on the linux-sunxi A133 page, a community wiki. LCSC hosts the A133 product brief and the R818 Datasheet Rev 1.5 (2020-08-12), which covers the same silicon. Allwinner does not publish them on a page our tools could reach, and its hardware design guides and reference schematics are not public.
Same die (sun50iw10), sorted by speed bin and market. The A133 datasheet gives 1.6 GHz and -20 to 70 C; the R818 datasheet has the identical feature list but -40 to 85 C ambient and targets smart displays; linux-sunxi reports the A133P as a 2.0 GHz bin and the A100 as the lowest bin (mainline caps it at 1.464 GHz). Software treats them all as sun50i-a100.
No. Outputs are one 4-lane MIPI DSI, dual-link LVDS or RGB up to 1920 x 1200 at 60 fps. There is no PCIe, SATA or USB 3; I/O tops out at one USB 2.0 OTG, one USB 2.0 host and one GbE MAC. HDMI needs an external bridge from DSI or RGB.
Headless only. CPU, clocks, pins, thermal, MMC, USB, Ethernet, LEDC and LRADC are upstream (5.10 to 7.3), with the Liontron H-A133L as the first board in 6.16, and mainline U-Boot has open DRAM init since v2025.10. Display, GPU, video engine, audio and camera are not upstream as of 7.3-rc7, so a product with a screen still runs Allwinner's BSP or Android.
Allwinner pairs it with the AXP707, which linux-sunxi lists as the AXP803 under another name; every mainline A133 board DT uses an AXP803 with DCDC2 on VDD_CPU and DCDC5 on DRAM. MangoPi's mCore-R818 module uses an AXP717. The AXP803 datasheet (Rev 1.0) is hosted by Pine64.
The MangoPi mCore-R818 (32 x 32 mm, AXP717, up to 4 GB LPDDR4) has module schematic PDFs and an Altium reference carrier with Gerbers. The Baijie A133 Core stamp-hole module has mainline DT support but no published files; the A-Pocket handheld project publishes a KiCad carrier for it. We found no A133 SoM from Forlinx, MYIR, Boardcon or Olimex.
Related chips and reading
- A64Open-hardware SBCs, Linux phones and laptops, kiosks, education
- H618 / H616Pi Zero class SBCs, CM4-style 3D-printer SoMs, TV boxes, retro handhelds (H700)
- A527 / T527Industrial HMI, dual-display terminals, gateways, robots, tablets
- T113HMI panels, CAN gateways, car displays, small Linux controllers
- RK3326 / PX30Handhelds, HMI panels, smart audio, kiosks
- RK3562Cost-down HMI, tablets, industrial gateways
- RK3566HMI, e-ink readers, handhelds, CM4-class SoMs, small routers
We'll design your A133 board.
Tell us the interfaces, power budget and volume. An engineer replies with questions or a proposal.
Links and facts on this page checked 2026-10-13. Spotted something out of date? Tell us through the contact form.
Compiled from publicly available sources: datasheets, technical reference manuals, vendor product pages, schematics and source code published by their owners and third parties. We link to documents where others host them and do not host, endorse or vouch for them. Everything on these pages, including our own specs, summaries, block diagrams, comparisons, calculators and design notes, is for reference only and may contain errors or be out of date. It is provided as is, and Groundplane is not responsible for errors in it, for third-party documents, or for any design, board or decision based on it. Always check the manufacturer's current datasheet, reference manual and design guidance before you design a board. Rockchip, Allwinner, Raspberry Pi and other product names are trademarks of their owners; we are not affiliated with any of them. See our disclosure.