H6
Quad Cortex-A53 4K60 HDR set-top-box SoC from 2017 with USB 3.0, a GbE MAC plus an in-package 10/100 PHY and a 32-bit DDR3/DDR4/LPDDR3 bus; its PCIe 2.0 x1 lane is documented by linux-sunxi as broken, so treat it as a no-PCIe part.
- CPU
- 4x A53 up to 1.8 GHz
- GPU
- Mali-T720 MP2
- NPU
- None
- Video
- 4K60 H.265 Main10 dec (H.264, VP9 4K30), 1080p60 H.264 enc
- PCIe
- PCIe 2.0 x1 (broken, no mainline driver)
What the H6 is for
Right for
- 4K HDR media playback appliances: H.265 Main10 at 4K60 with HDR10/HLG processing and HDMI 2.0a with HDCP 2.2, and the mainline Cedrus driver decodes H.264, H.265 (8 and 10-bit), MPEG-2 and VP8 on this SoC
- Fully open boot chains: mainline U-Boot initializes LPDDR3 and DDR3 with open-source DRAM code, TF-A has a sun50i_h6 platform, and Crust replaces the AR100 power firmware, so no Allwinner binary is needed to boot
- Low-cost Linux boxes needing one USB 3.0 host port and Gigabit Ethernet: one GMAC (RGMII or RMII) plus an in-package 10/100 PHY
- Pay-TV and DVB receivers: four transport stream inputs with PID filtering and DVB-CSA descrambling, two ISO 7816 smart card readers, CIR receive and transmit
Wrong for
- Anything that depends on PCIe: linux-sunxi documents the controller as broken (only a 64 KB window into PCIe space at a time) and there is no PCIe node or driver in mainline Linux as of 7.3-rc7
- Camera or vision products: the only camera input is an 8/10-bit parallel CSI capped at 1080p30 video and 5 MP stills, with no MIPI CSI and no ISP, and the CSI is not in the mainline device tree
- Panel products: there is no MIPI DSI, LVDS or eDP; the only panel output is an 18-bit RGB interface up to 1080p60, and it shares Port D with the RGMII and CSI pins
- Designs needing DDR4 on a mainline boot chain: U-Boot's H6 DRAM driver supports LPDDR3 and DDR3 only and panics on any other type
- Encode-heavy products: the datasheet rates the encoder at H.264 1080p60 only, with no H.265 encode, and mainline has no H6 encoder driver
Cost and constraints
- Package is FBGA451, 15 x 15 mm at 0.65 mm pitch, routable on a 6-layer board (Boardcon states 6 layers for its 45 x 45 mm CMH6 module)
- Power is one AXP805 PMIC in every public design checked: DCDC-A and B dual-phased for VDD-CPU (5 A), DCDC-C for VDD-GPU, DCDC-D for VDD-SYS, DCDC-E for DRAM, plus ten LDOs for the I/O rails
- Datasheet DRAM ceiling is 2 GB of address space on a 32-bit bus, although the user manual maps 3 GB of DRAM and Pine64 and Beelink ship 3 GB boards
- Rated -20 to +70 C ambient; no industrial-temperature H6 appears in any document found
- No bare-chip retail listing: JLCPCB carries H6 V200 as an assembly-only extended part (C5223989) with no stock shown, and LCSC has no product page for it; supply today is mainly through finished boards and modules
Inside the H6
Drawn by Groundplane from the datasheet rev 1.1. Not Allwinner artwork.
- 32-bit DDR3/DDR4/LPDDR3
- eMMC 5.1 (8-bit)
- SD 3.0, SDIO 3.0
- 8-bit NAND
- SPI NOR
- 4x Cortex-A53
- 32 KB L1 I/D per core
- 512 KB shared L2
- NEON, VFPv4, LPAE
- Mali-T720, 2 shader cores
- OpenGL ES 3.1, OpenCL 1.2
- H.265 4K60 decoder
- H.264 and VP9 4K30 decoder
- H.264 1080p60 encoder
- JPEG encoder
- IOMMU for DE, VE, CSI
- 32-bit DRAM controller
- DDR3/DDR4/LPDDR2/LPDDR3
- NAND controller, 80-bit ECC
- DE3.0, HDR10 and HLG
- HDMI 2.0a TX, HDCP 2.2
- RGB LCD timing controller
- TV encoder (CVBS)
- Parallel CSI, 8/10-bit
- TrustZone, secure boot
- Crypto engine, TRNG
- Disk encryption engine
- 4 Kbit eFuse
- AR100 management core
- CCU, 11 PLLs
- 16-ch DMA, timers, watchdog
- 2 thermal sensors
- Audio hub, 4x I2S/PCM
- Stereo DAC and ADC codec
- S/PDIF, 8-ch DMIC
- USB 3.0 host
- USB 2.0 host, USB 2.0 OTG
- PCIe 2.0 x1
- GbE MAC (RGMII/RMII)
- 10/100 Ethernet PHY
- HDMI 2.0a, CVBS out
- 18-bit RGB LCD
- Parallel CSI, 4x TS in
- I2S, S/PDIF, DMIC, line out
- UART x5, TWI x4, SPI x2, SCR x2
Read from the documents
Each value names the document it was read from.
| CPU | 4x Cortex-A53, 32 KB L1 I/D per core, 512 KB shared L2, NEON, VFPv4, LPAE, TrustZone | Datasheet Rev 1.1, 2.1 |
|---|---|---|
| CPU clock | Up to 1.8 GHz in the mainline OPP table (480 MHz to 1.8 GHz, three efuse speed bins); the datasheet states no clock | Other v7.3-rc7 |
| GPU | Mali-T720 with two shader cores (Midgard); OpenGL ES 3.1/3.0/2.0/1.1, OpenCL 1.2/1.1, DirectX 11 FL9_3, ASTC; mainline GPU OPP table tops out at 756 MHz | Datasheet Rev 1.1, 2.2 |
| Video decode | H.265 Main10 L5.1 4K60; H.264 BP/MP/HP L4.2 4K30; VP9 Profile 0/2 4K30; MPEG-1/2/4, H.263, VC-1, VP8, AVS/AVS+, Sorenson Spark, Xvid 1080p60; 1080p Blu-ray 3D | Datasheet Rev 1.1, 2.6.1 |
| Video encode | H.264 BP/MP/HP up to 1080p60; input up to 4800x4800, scaling 1/16 to 64x, rotated input | Datasheet Rev 1.1, 2.6.2 |
| JPEG | JPEG encode up to 4080x4080 | Datasheet Rev 1.1, 2.6.2 |
| Memory | 32-bit DDR3, DDR3L, DDR4, LPDDR2, LPDDR3; DDR4 up to 933 MHz clock; 2 chip selects; datasheet states up to 2 GB address space | Datasheet Rev 1.1, 2.3.2 |
| Storage | SMHC0 SD 3.0 4-bit; SMHC1 SDIO 3.0 4-bit (150 MHz SDR at 1.8 V); SMHC2 eMMC 5.1 8-bit (150 MHz SDR, 100 MHz DDR at 1.8 V); 8-bit NAND with 80-bit/1 KB ECC; SPI NOR boot; full-disk encryption on eMMC and NAND | Datasheet Rev 1.1, 2.3.1 to 2.3.4 |
| Display | HDMI 2.0a TX up to 4K60, HDCP 2.2/1.4, CEC, HDR, 8/10-bit; 18-bit RGB LCD up to 1920x1080 at 60 fps; CVBS TV out (NTSC/PAL); HDMI and LCD can run at the same time; DE3.0 with HDR to SDR conversion | Datasheet Rev 1.1, 2.5 |
| Camera | Parallel 8/10-bit CSI with BT.656, up to 5 MP stills and 1080p30 video, 148.5 MHz pixel clock; no MIPI CSI, no ISP | Datasheet Rev 1.1, 2.7.1 |
| PCIe | 1x PCIe 2.0 x1 (5 GT/s), root complex only, embedded PHY, 256-byte max payload | Datasheet Rev 1.1, 2.10.9 |
| USB | 1x USB 3.0 host (5 Gbps), 1x USB 2.0 host, 1x USB 2.0 OTG (also the FEL download port) | Datasheet Rev 1.1, 2.10.1 |
| Ethernet | 1x GMAC 10/100/1000, RGMII or RMII, jumbo frames to 16 KB; plus an in-package 10/100 EPHY with EEE and Wake-on-LAN | Datasheet Rev 1.1, 2.10.7, 2.10.8 |
| Audio | Up to 4 I2S/PCM with TDM (one for HDMI, one for the codec), audio hub crossbar, S/PDIF in/out, 8-channel DMIC; in-package codec with stereo DAC (100 dB SNR) and 2-channel ADC (92 dB SNR) | Datasheet Rev 1.1, 2.8 |
| Security | TrustZone, secure boot, crypto engine (AES, DES, 3DES, XTS, MD5, SHA-1/224/384/512, HMAC, RSA to 4096-bit, ECC to 521-bit), 256-bit TRNG, 4 Kbit eFuse, HDCP 2.2, DRM, transparent RAM scrambling | Datasheet Rev 1.1, 2.4.10 to 2.4.12, 2.9 |
| Other I/O | 5x UART (RS-485, IrDA), 2x SPI (quad), 4x TWI, 4x TS input with DVB-CSA descrambling, 2x ISO 7816 smart card, CIR RX and TX, 1-Wire, PWM, 16-channel DMA | Datasheet Rev 1.1, 2.4, 2.10 |
| Package | FBGA451, 15 x 15 mm, 0.65 mm ball pitch | Datasheet Rev 1.1, 2.11 |
| Temperature | Ambient -20 to +70 C; junction -20 to +125 C | Datasheet Rev 1.1, Table 5-2 |
| Thermal | theta-JA 23.1, theta-JB 11.97, theta-JC 8.07 C/W (JEDEC JESD51, 2s2p board, natural convection) | Datasheet Rev 1.1, 5.8, Table 5-24 |
Variants
| H6 V200 | The part name on Allwinner's datasheet and user manual (both Rev 1.1, 2017-10-17); boards and Allwinner's brief call it H6. No other H6 ordering code, speed grade or temperature grade appears in either document. | Datasheet Rev 1.1 |
|---|
What to watch when you design with it
Power and PMIC
Both public Pine64 schematics (PINE H64 Rev 1.1 and Model B Rev 1.2) power the H6 from a single X-Powers AXP805 on a 5 V input. Their power tables put VDD-CPU on DCDC-A and B in dual phase (5 A), VDD-GPU on DCDC-C (2.5 A), VDD-SYS, USB, HDMI and PCIe 0.9 V on DCDC-D, the DRAM rail on DCDC-E, and the 3.3 V and 1.8 V I/O, PLL, HDMI, PCIe and eFuse rails on ALDO1 to 3, BLDO1 to 3 and CLDO1. The AXP805 datasheet gives DCDC-A/B/C up to 2.5 A each (5 A dual-phase, 7.5 A tri-phase) and DVM on DCDC-A, C and D. The H6 datasheet's recommended VDD-CPU range is 0.81 to 1.08 V, but the mainline OPP table runs 1.488 GHz at 1.00 to 1.06 V and 1.8 GHz at 1.10 to 1.16 V depending on the efuse speed bin, so size the CPU rail and its thermal path for the higher figure if you ship the 1.8 GHz point. Pine64 rates its boards at 1488 MHz.
Sources: Board schematic Rev 1.1, Board schematic Rev 1.2, PMIC Rev 1.0, Datasheet Rev 1.1, Other v7.3-rc7, pine64.org
Power sequencing
The datasheet's power-up sequence: VCC-RTC first and kept on, VDD-CPUS with or after it, the 32 kHz clock running and stable, then VDD-SYS and VDD-CPUS ramping together before any other domain, with RESET held low until every rail is within 90 to 110 percent of nominal. On power-down the PMIC pulls RESET low first and the rails then fall together.
Sources: Datasheet Rev 1.1, Board schematic Rev 1.2
DDR
One 32-bit channel with two chip selects. The datasheet lists DDR3, DDR3L, DDR4, LPDDR2 and LPDDR3, with DDR4 clocked up to 933 MHz, and I/O supply ranges of 1.2 V (DDR4, LPDDR2, LPDDR3) or 1.5 V (DDR3, DDR3L) plus a 1.8 V VDD18-DRAM. Every public SBC checked uses a single x32 LPDDR3 part (Pine64, Orange Pi); the Tanix TX6 box uses DDR3. If you need mainline U-Boot, choose LPDDR3 or DDR3: its dram_sun50i_h6 driver has DDR4 marked TODO and panics on other types, with Kconfig timing presets only for H6 LPDDR3 and DDR3-1333. DQ swap and length rules are in Allwinner's hardware design guide, which is not on any linkable host; copy a vendor layout or ask your Allwinner agent.
Sources: Datasheet Rev 1.1, Board schematic Rev 1.2, Other, github.com
High-speed interfaces
USB 3.0 is a single host port with its own PHY; Orange Pi 3 fans it out to four ports through a hub, while Orange Pi 3 LTS, Lite 2 and Pine H64 bring out one. Plan on not using PCIe: linux-sunxi documents that the controller maps only 64 KB of PCIe space to the CPU at a time, so config, I/O and memory accesses must be wrapped, which a generic Linux driver cannot do; the BSP patches individual drivers, and an out-of-tree wrapped driver for Orange Pi 3 exists. Port D carries the RGB LCD, parallel CSI, TS0 and RGMII functions on shared pins, so a board gets Gigabit Ethernet or a parallel panel on those pins, not both (Boardcon's EMH6 lists its RGB LCD as multiplexed with the 1000M Ethernet). The in-package 10/100 PHY gives a second, slower Ethernet port without using Port D.
Sources: Datasheet Rev 1.1, Other, github.com, boardcon.com
Boot and FEL
The BootROM boots from SD (SMHC0), eMMC (SMHC2), NAND or SPI NOR. With the BOOT_MODE eFuse unset, one boot-select pin picks the order: SMHC0, NAND, SMHC2, SPI NOR or SMHC0, SMHC2, NAND, SPI NOR. If the FEL pin (labeled UBOOT on the Pine64 schematics) is held low at reset the ROM enters the mandatory upgrade path, which includes USB FEL on the USB 2.0 OTG port; high means normal media boot. Bring out a button or test point on that pin and keep the OTG port reachable. Pine H64 adds 128 Mbit of SPI NOR so the board can boot without an SD card.
Sources: TRM Rev 1.1, Board schematic Rev 1.2, pine64.org
Thermal
theta-JA 23.1 C/W, theta-JB 11.97 C/W and theta-JC 8.07 C/W on a JEDEC 2s2p board in still air, with an ambient rating of -20 to +70 C and Tj to 125 C. Two on-chip sensors cover the CPU and the GPU, and mainline has supported them since 5.6. The linux-sunxi Orange Pi 3 LTS page reports random freezes under a desktop load that it works around by pinning the GPU to one OPP.
Sources: Datasheet Rev 1.1, Other v7.3-rc7, linux-sunxi.org
Gotchas
linux-sunxi reports that some H6 chips have a watchdog that does not reset the SoC. The Ethernet PHY on Orange Pi 3 can fail after a reboot because U-Boot and TF-A do not cycle its regulators, so TF-A has to be built with SUNXI_SETUP_REGULATORS=0. Orange Pi 3 LTS replaces the RTL8211E with a Motorcomm YT8531C and has no mainline device tree yet (posted 2025-04-13, not merged by 7.3-rc7). The datasheet marks the EPHY, audio codec and TV encoder as "controlled by ATE", and none of them is in the mainline device tree.
Sources: Other, linux-sunxi.org, lore.kernel.org, Datasheet Rev 1.1, Other v7.3-rc7
Layout guides for the H6's interfaces
Public layout guidance for each interface this chip has, from vendors who publish it, plus our calculators.
DDR4
DDR4 uses pseudo open-drain data signaling and needs a VPP supply, with command/address routed fly-by or as a balanced tree depending on device count. TI AM62x uses 40 ohm single-ended and 80 ohm differential; AMD Versal uses 50 and 90 ohm, relaxed under the BGA. Match data to strobe per byte and command/address to clock.
- AM62x, AM62Lx DDR Board Design and Layout GuidelinesTexas Instruments, SPRAD06, C, 2025
- Versal Adaptive SoC PCB Design User Guide: PCB Routing Guidelines for DDR4 InterfacesAMD, UG863, 1.12, 2026
- SL1640 General PCB Design and DDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001529-01, D
- PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex 5 FPGAs and SoCsAltera, 821801, 2026
- DDR length matching calculatorGroundplane calculator
- Via current calculatorGroundplane calculator
DDR3 / DDR3L
Fly-by command/address with termination at the end of the chain, point-to-point data lanes matched to their strobe, and a clean VREF. ST recommends 55 ohm single-ended and 100 ohm differential for DDR3 and DDR3L on STM32MP1 boards, and shows that a 4-layer board is possible with strict layer allocation.
- STM32MP1 Series DDR memory routing guidelinesSTMicroelectronics, AN5122, 3, 2019
- DDR3 Design Requirements for KeyStone DevicesTexas Instruments, SPRABI1, D, 2022
- SL2610 General PCB Design and DDR3L/DDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001629-01, A, 2025
- DDR length matching calculatorGroundplane calculator
LPDDR3
Point-to-point and normally unterminated, with command/address matched to the clock and each byte matched to its strobe. ST gives the same targets for LPDDR3 as for DDR3: 55 ohm single-ended and 100 ohm differential. Few current public guides cover LPDDR3, so treat the SoC vendor's reference layout as the stronger source.
- STM32MP1 Series DDR memory routing guidelinesSTMicroelectronics, AN5122, 3, 2019
- DDR length matching calculatorGroundplane calculator
eMMC
A single-ended bus: CLK, CMD, DAT0 to DAT7 and, for HS400, the data strobe. TI and Synaptics both route it at 50 ohm single-ended, match the group, and keep stubs short; Synaptics places a 22 or 33 ohm series resistor on CLK and STRB. At HS400 TI also checks the eMMC I/O supply impedance, not just the traces.
- AM62Px eMMC HS400 Board Design and Simulation GuidelinesTexas Instruments, SPRADP5, A, 2026
- Astra Machina Foundation Series eMMC ConfigurationSynaptics, PN 506-001594-01, D
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
SD card / SDIO
Single-ended CLK, CMD and four data lines over a solid ground plane, at constant trace width and matched length. NXP asks for clock-to-neighbor spacing greater than twice the trace height above the plane and 1.5 times for data and CMD, with 45 degree bends. UHS modes switch the I/O to 1.8 V, so a level translator often sits next to the socket.
- NVT4557/NVT4558/NVT4858 voltage-level translator layout guidelineNXP, AN13158, 1.1, 2022
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
- SD Physical Layer Simplified SpecificationSD Association, 9.10, 2023
PCIe
AC-coupled differential lanes routed with no stubs, minimal vias and back-drilled or blind vias where speed demands, with lane-to-lane skew handled by the receiver. Targets differ by guide: TI Jacinto 7 uses 85 ohm differential for lanes and 100 ohm for the reference clock, while TI's earlier SoC guide tabulates 100 ohm and, for some devices, 95 ohm. Match the target to your connector and stackup.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
USB 3.x
SuperSpeed TX and RX pairs are routed at 90 ohm differential in all three TI guides (SPRAAR7 lists 95 ohm for some devices), with AC coupling capacitors on TX, symmetric pad and via placement, and matched via counts within each pair. Keep the pairs away from the USB 2.0 pair and other aggressors, and place ESD at the connector.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
USB 2.0
One D+/D- pair at 90 ohm differential, routed in parallel for its whole length with minimal deviations at the connector and package. NXP keeps clocks and periodic signals at least 50 mils away and other signals at least 20 mils away from the pair.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
HDMI
Four TMDS pairs (three data, one clock) at 100 ohm differential, as both TI guides state, with tight intra-pair matching and as few vias as possible between the SoC and the connector. HDMI also needs 5 V supply switching, DDC and CEC level handling, hot-plug detect and ESD at the connector.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- TPD12S016 PCB Layout Guidelines for HDMI ESDTexas Instruments, SLLA324, 2012
MIPI CSI-2
Same D-PHY rules as DSI: 100 ohm differential lanes in both TI guides, with lane-to-lane skew bounded (40 ps in TI Jacinto 7). Size the lane count and lane rate from the sensor's output format before routing.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex 5 FPGAs and SoCsAltera, 821801, 2026
- MIPI CSI-2 bandwidth calculatorGroundplane calculator
Ethernet (RGMII / RMII)
TI routes MAC-to-PHY (MII family) traces at 50 ohm single-ended, under 6 inches, matched within 20 mils for gigabit, and the PHY-side MDI pairs at 100 ohm differential. RGMII also needs a 1.5 to 2.0 ns clock-to-data delay, added on the board or inside the MAC or PHY (RGMII-ID); decide which before layout so it is not applied twice.
- Ethernet PHY PCB Design Layout ChecklistTexas Instruments, SNLA387, 2021
- PCB Design Guideline for RGMII InterfaceRenesas, R01AN6272EJ0141, 1.41, 2026
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
Board-level design guides
Impedance and timing, power, thermal and ESD guidance that applies to any board around this chip.
Impedance and timing
Every high-speed interface on the board comes down to the same two numbers: the trace impedance your stackup actually gives, and the delay each trace adds. Set the stackup with your fab first, then route to its impedance table and match lengths in time, not millimeters, where the layers differ.
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- PCB impedance calculatorGroundplane calculator
- PCB propagation delay calculatorGroundplane calculator
Power delivery
For each switching regulator, place and route the input capacitor first, keep the switching current loop small, and keep the switch node short. Give the SoC rails solid planes and decoupling at the balls, and size current-carrying copper and vias for the real load.
- Five steps to a great PCB layout for a step-down converterTexas Instruments, SLYT614, 2015
- AN-1149 Layout Guidelines for Switching Power SuppliesTexas Instruments, SNVA021, C, 2013
- AN-1229 SIMPLE SWITCHER PCB Layout GuidelinesTexas Instruments, SNVA054, C, 2013
- Buck converter calculatorGroundplane calculator
- LDO power dissipation calculatorGroundplane calculator
- PCB trace width calculatorGroundplane calculator
- Via current calculatorGroundplane calculator
Thermal
Theta-JA is measured on a JEDEC test board that carries most of the heat, so it does not transfer directly to a product board; use it to compare packages and use the psi metrics for estimates. Thermal vias under the package, copper area and copper thickness move the most heat into the board.
- Semiconductor and IC Package Thermal MetricsTexas Instruments, SPRA953, D, 2024
- AN-2020 Thermal Design By Insight, Not HindsightTexas Instruments, SNVA419, C, 2013
- Heatsink thermal resistance calculatorGroundplane calculator
- LDO power dissipation calculatorGroundplane calculator
ESD protection
Place the TVS as close to the connector as design rules allow, route from the connector to the TVS with no stub, and keep the protected IC further from the TVS than the TVS is from the connector. Choose parts by clamping performance and by capacitance low enough for the interface speed.
- ESD Protection Layout GuideTexas Instruments, SLVA680, A, 2022
- Reading and Understanding an ESD Protection Data SheetTexas Instruments, SLLA305, A
- TPD12S016 PCB Layout Guidelines for HDMI ESDTexas Instruments, SLLA324, 2012
- PCB conductor spacing calculator (IPC-2221)Groundplane calculator
Allwinner's hardware design guide
Allwinner's hardware design guide, EVB reference schematics and DDR templates come from Allwinner or an authorized agent, usually under NDA, or through your SoM vendor. We do not link copies circulating elsewhere. The vendor schematics and open designs on the Boards tab are real, shipped layouts on the H6 and the best public reference.
BSP, mainline and toolkits
| Area | Status | Links |
|---|---|---|
| Vendor BSP kernel | Allwinner's H6 SDKs ship Linux 3.10.65 (Lichee v1.1, Android 7) and a Linux 4.9 BSP (Allwinner-Homlet repos marked "beta version, not final release", last pushed 2018). Pine64 hosts a Linux 4.9 BSP SDK and an Android 9 SDK for the H64 Model B; Orange Pi keeps an orange-pi-4.9-sun50iw6 branch. Boardcon ships Android 7 on Linux 3.10.65 for CMH6 and EMH6.Checked 2026-10-13 | |
| Mainline Linux | SoC dtsi and Pine H64 in 4.17; MMC in 4.19; display engine DE3, HDMI and EMAC in 5.0; Cedrus video engine and SID in 5.2; DMA and watchdog in 5.3; S/PDIF and RTC in 5.4; USB 3.0 (DWC3), Mali-T720 GPU node for Panfrost and crypto engine in 5.5; thermal sensors and PWM in 5.6; IOMMU and the CPU DVFS OPP table in 5.8; HDMI audio I2S in 5.11; Hantro G2 VP9 decoder in 5.17 (staging, out of staging in 6.1); a GPU OPP table in 6.1, used only by the Beelink GS1 and TaiqiCat A01 device trees. Not upstream as of 7.3-rc7: PCIe, the parallel CSI, the in-package 10/100 PHY, analog audio codec and TV encoder, and any H6 video encoder. Board device trees: Pine H64 and Model B, Orange Pi 3, One Plus and Lite 2, Beelink GS1, Tanix TX6 and TX6 mini, and TaiqiCat A01 (added in 7.1).Checked 2026-10-13 | |
| U-Boot | Mainline U-Boot supports the H6 since v2018.09 (Pine H64), with board maintainers for Pine H64, Orange Pi 3 (since v2021.04), One Plus, Lite 2, Beelink GS1 and Tanix TX6. DRAM init is open source (dram_sun50i_h6.c) but covers LPDDR3 and DDR3 only.Checked 2026-10-13 | |
| TF-A and SCP firmware | TF-A has a plat/allwinner/sun50i_h6 platform. Crust, the open firmware for the AR100 management core, lists the H6 as production/stable with SCPI, CPU, DRAM and PMIC support, and ships defconfigs for Pine H64, Orange Pi 3, Tanix TX6 and Beelink GS1; its README notes that most H6 boards need a Linux kernel with commit 531fdbeedeb8 for the default PMIC bus setting.Checked 2026-10-13 | |
| Video | Mainline: Cedrus (stateless V4L2, still in staging) lists H.264, H.265 8 and 10-bit, MPEG-2 and VP8 decode for the H6; VP9 goes through the Hantro G2 driver (drivers/media/platform/verisilicon). No encoder. Vendor: Allwinner's CedarX/libcedarc userspace on the BSP kernel.Checked 2026-10-13 | |
| Android | Vendor images only: Android 7 (Allwinner H6 SDK on Pine64; Orange Pi 3, One Plus and Lite 2; Boardcon), Android 9 (Pine64 SDK; Orange Pi 3 LTS; Tanix TX6 firmware).Checked 2026-10-13 | |
| Distributions | Armbian: Orange Pi 3 LTS at standard support; Orange Pi 3, One+, Lite 2, Pine H64 and H64 model B at community support; Tanix TX6 as a TV box image. Orange Pi ships Debian and Ubuntu through orangepi-build; Orange Pi's 3 LTS page also lists DietPi, Batocera, Manjaro and MainsailOS images.Checked 2026-10-13 | |
| Community | The linux-sunxi wiki (H6 chip page, per-board pages and the mainlining status tables), the Pine64 forum, and the Orange Pi forum.Checked 2026-10-13 |
H6 system on modules
Any of these can sit on a carrier board we design.
| Module | Vendor | Connector | RAM | Design files | Buy |
|---|---|---|---|---|---|
| CMH6 | Boardcon | 138-pin QFN-style edge pads, 1.25 mm pitch | 1 or 2 GB LPDDR3 | Pin definition table on the product page; no schematic found |
Every public H6 board
| Board | Vendor | Type | RAM | Notable I/O | Design files | Buy |
|---|---|---|---|---|---|---|
| PINE H64 Model A | Pine64 | SBC, 133 x 80 mm | 1, 2 or 3 GB LPDDR3 | mini PCIe connector, USB 3.0 host, 2x USB 2.0, GbE, HDMI 4Kp60, 128 Mbit SPI flash, eMMC module socket | Schematic PDF (Rev 1.1, 2018-01-04) and connector pin assignment PDF | |
| PINE H64 Model B | Pine64 | SBC, 85 x 56 mm | 1, 2 or 3 GB LPDDR3 | USB 3.0 host, 2x USB 2.0, GbE, HDMI 4Kp60, Wi-Fi 5, BT, 40-pin Pi-2 header, 128 Mbit SPI flash | Schematic PDF (Rev 1.2, 2018-12-12), pin assignment PDF, FCC and CE certificates | |
| Orange Pi 3 | Orange Pi | SBC | 1 or 2 GB LPDDR3 | 4x USB 3.0 (through a hub), GbE (RTL8211), HDMI 2.0a, CVBS, Wi-Fi 5, BT 5.0 (AP6256), Optional 8 GB eMMC | Schematic PDF v1.6 (Google Drive, linked from the vendor download page) | |
| Orange Pi 3 LTS | Orange Pi | SBC, 85 x 56 mm | 2 GB LPDDR3 | 8 GB eMMC, USB 3.0 host, 2x USB 2.0, GbE (YT8531C), HDMI 2.0a, CVBS, Wi-Fi 5, BT 5.0, USB-C power | Schematic PDF v1.4 and mechanical files (Google Drive, linked from the vendor download page) | |
| Orange Pi One Plus | Orange Pi | SBC, 68 x 48 mm | 1 GB LPDDR3 | GbE (RTL8211), HDMI 2.0a, USB 2.0 host, micro USB OTG, 26-pin header | Schematic PDF v2.0 (Google Drive, linked from the vendor download page) | |
| Orange Pi Lite 2 | Orange Pi | SBC, 69 x 48 mm | 1 GB LPDDR3 | USB 3.0 host, USB 2.0 host, micro USB OTG, Wi-Fi 5, BT 4.1 (AP6255), HDMI 2.0a, Parallel CSI camera connector | Schematic PDF v2.0 (Google Drive, linked from the vendor download page) | |
| EMH6 | Boardcon | Dev kit, 140 x 100 mm | 1 or 2 GB LPDDR3 | GbE (RTL8211E, shares pins with RGB LCD) and 10/100 Ethernet, HDMI 2.0a, CVBS, 2x eDP via NCS8801S, M.2 for NVMe or 4G, USB 3.0 host, USB 2.0 OTG | Block diagram and PCB dimension drawing on the product page; no schematic found | |
| Tanix TX6 / TX6 mini (TV box) | Tanix | SBC, TV box | 2 or 4 GB DDR3 (TX6) | 10/100 Ethernet, HDMI, USB 3.0 host | None | |
| Beelink GS1 (TV box) | Beelink | SBC, TV box, 100 x 100 mm | 2 or 3 GB LPDDR3 | GbE (RTL8211E), HDMI, S/PDIF, USB 3.0 host, USB 2.0 host | None |
Prices and links as checked on the dates in our data; the latest check on this page was 2026-10-13. Amazon links marked * are affiliate links; see our disclosure.
Buying the chip
No distributor listing for the bare H6 could be confirmed: JLCPCB lists H6 V200 (C5223989) for its own assembly service only, with no stock, and LCSC has no product page for that number. Boardcon sells the CMH6 module but publishes no bare-chip price. Pine64 lists the H64 Model A as discontinued and no H64 board is in its store.
- JLCPCB (assembly only)
- The parts library lists H6 V200, Allwinner Tech, FBGA451, as extended part C5223989 in its New Arrivals category; JLCPCB states such parts are kept for its own PCBA orders and cannot be shipped separately. No stock was shown on 2026-10-13 and the listed unit price (USD 0.04) is a placeholder, so no price is recorded. LCSC has no product page for C5223989.
- Allwinner direct
- The datasheet and brief give service@allwinnertech.com as the contact. Allwinner does not publish an authorized distributor list we could confirm.
Datasheet, TRM and design documents
Linked where they are publicly hosted; we do not rehost Allwinner documents. These are third-party documents: we are not responsible for their accuracy, availability or confidentiality status. Disclosure.
- DatasheetAllwinner H6 V200 DatasheetRev 1.1 · 2017-10-17 · hosted by Pine64 · checked 2026-10-13
- TRMAllwinner H6 V200 User ManualRev 1.1 · 2017-10-17 · hosted by Pine64 · checked 2026-10-13
- Product briefAllwinner H6 product briefV1.0 · 2017 · hosted by Pine64 · checked 2026-10-13
- PMICX-Powers AXP805 DatasheetRev 1.0 · 2017-11-14 · hosted by Pine64 · checked 2026-10-13
- Board schematicPine64 PINE H64 (Model A) schematic (H6 + AXP805 + LPDDR3)Rev 1.1 · 2018-01-04 · hosted by Pine64 · checked 2026-10-13
- Board schematicPine64 PINE H64 Model B schematic (H6 + AXP805 + LPDDR3)Rev 1.2 · 2018-12-12 · hosted by Pine64 · checked 2026-10-13
- Otherlinux-sunxi H6 chip page (features, errata, SDK links)hosted by linux-sunxi · checked 2026-10-13
- OtherLinux sun50i-h6.dtsi (mainline SoC device tree)v7.3-rc7 · hosted by kernel.org · checked 2026-10-13
- OtherLinux sun50i-h6-cpu-opp.dtsi (CPU OPP table, 480 MHz to 1.8 GHz)v7.3-rc7 · hosted by kernel.org · checked 2026-10-13
- OtherU-Boot dram_sun50i_h6.c (open-source H6 DRAM init)hosted by GitHub (u-boot) · checked 2026-10-13
Questions about the H6
Not the H6 itself. We have designed and brought up boards on the Allwinner T507 and A527/T527, and on the Rockchip RV1106, RV1126, RV1126B, RK3566, RK3568, RK3576 and RK3588. The work carries over: power tree, DDR and high-speed layout, bring-up and the BSP, read against this chip's own datasheet.
Pine64 hosts the H6 V200 Datasheet Rev 1.1 and User Manual Rev 1.1 (both 2017-10-17), the H6 product brief and the AXP805 PMIC datasheet on its PINE H64 datasheets page; the linux-sunxi H6 page links the same datasheet and manual. Rev 1.1 is the newest revision found. Allwinner's hardware design guide and reference schematics are not publicly hosted by Allwinner or a board vendor.
Not in any practical sense. The datasheet lists a PCIe 2.0 x1 root complex, but linux-sunxi documents the controller as mapping only 64 KB of PCIe address space at a time, so every access must be wrapped. The vendor BSP patches individual drivers, there is no PCIe support in mainline Linux as of 7.3-rc7, and the only working setups found are out-of-tree patches for Orange Pi 3.
Good for a headless or media box: CPU with DVFS, HDMI display and audio, Panfrost on the Mali-T720, USB 3.0, GbE MAC, eMMC/SD, thermal, crypto and IOMMU are upstream (4.17 to 5.11), Cedrus decodes H.264 and H.265 including 10-bit, and VP9 goes through Hantro since 5.17. Mainline U-Boot, TF-A and Crust give a boot chain with no Allwinner binaries. Missing: PCIe, the parallel camera, the in-package 10/100 PHY, analog audio, CVBS out and any encoder.
The X-Powers AXP805, on every public schematic checked (Pine H64 Model A and B) and on the Orange Pi product pages. The Pine64 designs dual-phase DCDC-A and B for a 5 A CPU rail, use DCDC-C for the GPU, DCDC-D for the 0.9 V system rail and DCDC-E for DRAM. The AXP805 datasheet Rev 1.0 is on Pine64.
The SoC supports DDR4 up to 933 MHz per the datasheet, but mainline U-Boot's H6 DRAM driver supports only LPDDR3 and DDR3. If you want an all-open boot chain, use LPDDR3 (as Pine64 and Orange Pi do) or DDR3 (as the Tanix TX6 does).
Related chips and reading
- H618 / H616Pi Zero class SBCs, CM4-style 3D-printer SoMs, TV boxes, retro handhelds (H700)
- A64Open-hardware SBCs, Linux phones and laptops, kiosks, education
- A527 / T527Industrial HMI, dual-display terminals, gateways, robots, tablets
- RK3328Routers, TV boxes, Klipper hosts
- RK3528TV boxes, media players, small routers
- RK3566HMI, e-ink readers, handhelds, CM4-class SoMs, small routers
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Links and facts on this page checked 2026-10-13. Spotted something out of date? Tell us through the contact form.
Compiled from publicly available sources: datasheets, technical reference manuals, vendor product pages, schematics and source code published by their owners and third parties. We link to documents where others host them and do not host, endorse or vouch for them. Everything on these pages, including our own specs, summaries, block diagrams, comparisons, calculators and design notes, is for reference only and may contain errors or be out of date. It is provided as is, and Groundplane is not responsible for errors in it, for third-party documents, or for any design, board or decision based on it. Always check the manufacturer's current datasheet, reference manual and design guidance before you design a board. Rockchip, Allwinner, Raspberry Pi and other product names are trademarks of their owners; we are not affiliated with any of them. See our disclosure.