D1 / D1s
Single-core 64-bit RISC-V (T-Head C906) media SoC for low-cost Linux HMI and display boards: 1080p60 to 4K30 decode, no GPU, no NPU, USB 2.0 only; D1s/F133 put 64 MB DDR2 in a 14 x 14 mm eLQFP128 so the board needs no external DRAM.
- CPU
- 1x C906 RISC-V 1.0 GHz
- GPU
- None (2D G2D only)
- NPU
- None
- Video
- D1-H: 4K30 H.265, 4K24 H.264 dec; D1s/F133: 1080p60 dec; JPEG/MJPEG enc 1080p60
- PCIe
- None
What the D1 / D1s is for
Right for
- Cheap RISC-V Linux targets where the ISA is the point: Nezha, Lichee RV, MangoPi MQ-Pro and ClockworkPi R-01 all have mainline device trees since Linux 6.3 or 6.11
- Display appliances on a 2-layer board: D1s/F133 carry 64 MB DDR2 in an eLQFP128 and drive RGB, dual-link LVDS or 4-lane MIPI DSI up to 1080p60 (Xassette-Asterisk is a 2-layer 56 x 56 mm D1s board)
- Audio front ends: on-chip codec with 2 DACs and 3 ADCs, up to 8 PDM microphones, I2S/TDM and S/PDIF, plus a 600 MHz HiFi4 DSP on D1-H
- HDMI media players at up to 4K30 H.265 decode on D1-H with the vendor Tina Linux BSP
Wrong for
- Anything needing a 3D GPU: there is none, only a 2D G2D blitter, so desktops run on software rendering
- High-speed I/O: no PCIe, no USB 3, no SATA; USB is two USB 2.0 ports and Ethernet is one GbE MAC
- Cameras beyond a parallel sensor: input is 8-bit parallel CSI and CVBS only, with no MIPI CSI and no ISP
- Hardware video decode or HDMI on mainline Linux: the cedrus driver knows the D1 but no video engine or HDMI node exists in the mainline device tree as of 7.3-rc7
- Mainstream RISC-V distributions going forward: Ubuntu 26.04 requires the RVA23 profile and keeps D1 boards on 24.04.5; the C906 vector unit is the pre-ratification 0.7.1 XTheadVector, not RVV 1.0
Cost and constraints
- Bare chip on LCSC: D1-H reference USD 5.23 at 119 (out of stock), D1s USD 4.80 at 90 (out of stock), F133-B USD 8.46 at 90 with 101 in stock; no Allwinner PMIC is used on any public board, so power is three or four discrete bucks
- D1-H: LFBGA337, 13 x 13 mm, 0.65 mm pitch, 16-bit DDR2/DDR3 up to 2 GB; Nezha is a 6-layer board
- D1s/F133: DRAM fixed at 64 MB in package; exposed pad on the eLQFP128 must use the 5.72 mm pad size called out in the datasheet
- Ambient rating is -25 to 85 C for D1-H but only -25 to 75 C for D1s/F133 (70 C when the internal LDO feeds the DRAM)
- Mainline boot still depends on out-of-tree pieces: no RISC-V D1 board in mainline U-Boot, DRAM init comes from smaeul/sun20i_d1_spl or the vendor boot0
Inside the D1 / D1s
Drawn by Groundplane from the datasheet v1.0. Not Allwinner artwork.
- 16-bit DDR2/DDR3 (D1-H)
- SD 3.0, SDIO 3.0
- eMMC 5.0
- SPI NOR or SPI NAND
- 1x XuanTie C906 RV64, 1 GHz
- 32 KB I-cache, 32 KB D-cache
- HiFi4 DSP 600 MHz (D1-H)
- No 3D GPU
- G2D 2D engine, 2048 x 2048
- H.265 4K30, H.264 4K24 decode
- JPEG/MJPEG encode 1080p60
- De-interlacer 1080p60
- 16-bit DDR2/DDR3, 2 GB (D1-H)
- 64 MB DDR2 in package (D1s/F133)
- Boot ROM
- Display engine, SmartColor 2.0
- TCON LCD and TCON TV
- HDMI 1.4 TX 4K30 (D1-H)
- 8-bit parallel CSI
- CVBS in, 1 decoder
- Crypto engine, TRNG
- 2 Kbit eFuse
- PLIC, 16-ch DMA, IOMMU
- Thermal sensor, RTC
- 2 internal LDOs
- Audio codec, 2 DAC, 3 ADC
- USB 2.0 DRD (FEL port)
- USB 2.0 host
- GbE MAC, RGMII or RMII
- HDMI 1.4 (D1-H)
- RGB, dual LVDS, MIPI DSI x4
- CVBS in and out, 8-bit CSI
- I2S x3, DMIC x8, S/PDIF
- UART x6, TWI x4, SPI x2, PWM x8
Read from the documents
Each value names the document it was read from.
| CPU | XuanTie C906 64-bit RISC-V, single core, 32 KB I-cache + 32 KB D-cache; HiFi4 DSP with 32 KB I/D cache and 64 KB I/D RAM (D1-H only) | Datasheet V1.0, 2.1, 2.2 |
|---|---|---|
| CPU clock | D1-H: 1 GHz (Allwinner Online "1GHz+"; mainline OPP table tops out at 1008 MHz). DSP 600 MHz. The datasheet itself states no CPU maximum | Product brief |
| GPU | None. 2D Graphic engine (G2D) up to 2048 x 2048 with rotate, scale, blend and LBC decompression | Datasheet V1.0, 2.5.3 |
| NPU | None | Datasheet V1.0, Features |
| Video decode | D1-H: H.265 MP@L5.0 up to 4K30, H.264 BP/MP/HP@L5.0 up to 4K24, H.263, MPEG-1/2/4, Xvid, Sorenson Spark, VC-1 up to 1080p60, MJPEG 1080p30. D1s/F133: same codecs up to 1080p60 | Datasheet V1.0, 2.4; D1s/F133 from ds-d1s and ds-f133 Features |
| Video encode | JPEG/MJPEG only, up to 1080p60, with input scaler; no H.264/H.265 encode | Datasheet V1.0, 2.4 |
| Memory | D1-H: 16-bit DDR2 (up to 533 MHz) or DDR3 (up to 800 MHz), 2 GB max. D1s/F133: 64 MB DDR2 in package, up to 533 MHz | Datasheet V1.0, 2.3.2, pin list SDQ0 to SDQ15; D1s/F133 from ds-d1s 2.2.2 and ds-f133 |
| Storage | Three SD/MMC hosts: SD 3.0 (SMHC0), SDIO 3.0 (SMHC1), eMMC 5.0 (SMHC2), 150 MHz SDR at 1.8 V; boot from SD, eMMC, SPI NOR or SPI NAND | Datasheet V1.0, 2.3.1, 2.3.3 |
| Display | RGB up to 1920 x 1080 at 60 Hz, dual-link LVDS 1920 x 1080 at 60 Hz, 4-lane MIPI DSI v1.01 up to 1920 x 1200 at 60 Hz, i8080 and SPI DBI panels, CVBS out; HDMI 1.4 TX up to 4K30 on D1-H only. Display engine output up to 2048 x 2048 | Datasheet V1.0, 2.5.1, 2.6 |
| Camera | 8-bit parallel CSI (RAW8, YUV422/420, BT.656/BT.601), 148.5 MHz pixel clock; 2-channel CVBS in with one decoder (not on F133-A). No MIPI CSI, no ISP | Datasheet V1.0, 2.7; F133-A from ds-f133 Table 1-1 |
| PCIe | None | Datasheet V1.0, Features |
| USB | 1x USB 2.0 DRD (USB0, host or device, used for FEL) and 1x USB 2.0 host (USB1), both with integrated PHY | Datasheet V1.0, 2.11.1, 2.11.2 |
| Ethernet | 1x EMAC, 10/100/1000 with RGMII or RMII to an external PHY | Datasheet V1.0, 2.11.3 |
| Audio | Codec with 2 DACs (to 192 kHz) and 3 ADCs (to 48 kHz), headphone and differential line out, 3 mic inputs; 3x I2S/PCM/TDM (2x on D1s/F133), up to 8 PDM mics, S/PDIF (OWA) TX and RX (TX only on F133) | Datasheet V1.0, 2.9; D1s/F133 from ds-d1s 2.8.2 and ds-f133 Features |
| Security | Crypto engine: AES, DES/3DES, RSA up to 2048, MD5, SHA-1/2, HMAC, TRNG; 2 Kbit eFuse (SID) | Datasheet V1.0, 2.10 |
| Other I/O | 6x UART, 2x SPI (SPI1 with DBI), 4x TWI, 8x PWM, CIR RX and TX, 2-ch GPADC (1-ch on D1s/F133), 4-ch TPADC, LRADC (D1-H), LEDC for addressable LEDs, 2 internal LDOs | Datasheet V1.0, 2.8, 2.11; D1s from ds-d1s 2.10 |
| Process | 22 nm | Product brief |
| Package | D1-H: LFBGA337, 13 x 13 mm, 0.65 mm pitch, 0.35 mm balls, MSL3. D1s/F133: eLQFP128 with exposed pad, 14 x 14 x 1.4 mm, MSL3 | Datasheet V1.0, 2.12, 8.2.1; D1s/F133 from ds-d1s Features and 8.2.1 |
| Temperature | D1-H: ambient -25 to 85 C, Tj -20 to 125 C absolute maximum (recommended Tj maximum left TBD). D1s/F133: ambient -25 to 75 C (70 C with internal LDO feeding DRAM), Tj -25 to 110 C | Datasheet V1.0, Table 5-1, Table 5-2; D1s/F133 from ds-d1s and ds-f133 Table 5-2 |
| Thermal | D1s/F133: theta-JA 20.36, theta-JB 7.43, theta-JC 5.52 C/W (JESD51). D1-H values are TBD in the datasheet. One on-chip thermal sensor | Datasheet V1.0, Table 6-1 |
Variants
| D1-H (D1) | Base part: C906 plus 600 MHz HiFi4 DSP, external 16-bit DDR2/DDR3 up to 2 GB, HDMI 1.4 TX up to 4K30, H.265 decode to 4K30, 3x I2S, LFBGA337 13 x 13 mm. Early documents (Datasheet V0.1, 2021-03-02) call it simply D1. | Datasheet V1.0 |
|---|---|---|
| D1s | 64 MB DDR2 in package (no external DRAM bus), no HDMI, no HiFi4 DSP, decode capped at 1080p60, 2x I2S, 1-ch GPADC, no LRADC, eLQFP128 14 x 14 mm. Ambient rating drops to 75 C. The datasheet calls the core a "RISC CPU"; Allwinner Online names it C906. | Datasheet V1.0 |
| F133-A | Same die and eLQFP128 package as D1s (64 MB DDR2 in package, 1080p60 decode, RGB/LVDS/DSI out). Pins 107 to 111 are NC: no CVBS input. S/PDIF is TX only. 99 I/O pins. | Datasheet V2.1 |
| F133-B | As F133-A but with CVBS input on pins 107 to 111 (VCC-TVIN, TVIN0, TVIN1, TVIN-VRP, TVIN-VRN). This is the part LCSC stocks. | Datasheet V2.1 |
| T113 (sibling) | Mainline Linux describes D1s and T113 peripherals with one shared device tree include (sunxi-d1s-t113.dtsi); T113 swaps the RISC-V core for dual Cortex-A7 and has its own page. | Other |
What to watch when you design with it
Power and PMIC
No public D1 board uses an Allwinner PMIC; every schematic checked builds the tree from discrete bucks. Allwinner Online lists the Nezha PMIC as discrete parts, the Lichee RV uses three TMI3411 bucks, the ClockworkPi R-01 module uses SY8088AAC and SY8089A1AAC and the MangoPi MQ-Pro an MP2122 dual buck. The datasheet gives VDD-CPU and VDD-SYS at 0.9 V typical (CPU voltage depends on frequency), VCC-DRAM at 1.8 V for DDR2 or 1.5 V for DDR3, and two internal LDOs fed from 2.4 to 3.6 V: LDOA 1.8 V for I/O and analog, LDOB 1.35/1.5/1.8 V able to supply the DRAM. Power-on order: VCC-RTC no later than any other rail, VCC-IO at least 2 ms before VDD-SYS and VDD-CPU, RESET held low until all rails have been stable for more than 64 ms.
Sources: Datasheet V1.0, Other, Board schematic Rev 1.0, Board schematic, Board schematic v1.2
DDR
D1-H has a 16-bit DRAM bus (SDQ0 to SDQ15, two byte lanes) for DDR2 up to 533 MHz or DDR3 up to 800 MHz, 2 GB maximum. The Lichee RV and MQ-Pro use a single x16 DDR3 device. Sipeed specifies the Lichee RV DDR3 at up to 792 MHz. D1s and F133 remove the problem entirely with 64 MB of DDR2 in the package; that is what lets Xassette-Asterisk fit a D1s/F133 board on 2 layers, while Nezha (external DDR3, BGA) is a 6-layer board. DRAM training for mainline boot comes from smaeul/sun20i_d1_spl or from the vendor boot0, not from mainline U-Boot.
Sources: Datasheet V1.0, Board schematic Rev 1.0, Other, wiki.sipeed.com, github.com, github.com
High-speed interfaces
There is no SerDes: no PCIe, USB 3 or SATA. The fastest board-level interfaces are RGMII to a GbE PHY (RTL8211F on Nezha), HDMI 1.4 with a TMDS clock up to 340 MHz on D1-H, a 4-lane MIPI DSI, dual-link LVDS and two USB 2.0 ports. Wi-Fi goes on SDIO (XR829 on Nezha and Lichee RV boards, RTL8723DS on MQ-Pro). On the Lichee RV the RGB interface is partly multiplexed with DSI, so choose one panel type per design.
Sources: Datasheet V1.0, Other, Board schematic v1.2, wiki.sipeed.com
Boot and FEL
The BROM boots from SD (SMHC0), eMMC (SMHC2), SPI NOR or SPI NAND. A BOOT_MODE eFuse bit picks between eFuse-programmed boot order and pin strapping; with pins, BOOT-SEL[1:0] on PC4/PC5 select 00 SPI NOR then NAND, 01 SD then SPI NOR, 10 SD then SPI NAND, 11 SD then eMMC. PC4/PC5 are also SPI0 and eMMC data pins, which is why the Lichee RV schematic warns not to use them as GPIO. On D1-H, pulling the FEL ball (A18) low forces the USB FEL download mode on the USB0 OTG port; the BROM flow also falls into this mode when media boot fails. The D1s/F133 pin lists show BOOT-SEL on PC4/PC5 but no FEL pin. xfel supports D1 and F133 for DRAM init and loading code over FEL.
Sources: TRM V1.0, Datasheet V1.0, Datasheet V1.0, Board schematic Rev 1.0, github.com
Thermal
D1s/F133 in eLQFP128 have theta-JA 20.36 C/W, theta-JB 7.43 C/W and theta-JC 5.52 C/W, with most heat leaving through the exposed pad, so solder it to a ground pour with vias. The D1-H datasheet leaves all three thermal resistances as TBD. Junction limits are 125 C absolute maximum for D1-H (its recommended maximum is TBD) and 110 C for D1s/F133. One on-chip sensor sits in the CPU (plus or minus 3 C from 0 to 100 C); its mainline driver arrived in 6.8 and the device tree node in 7.0.
Sources: Datasheet V1.0, Datasheet V2.1, Datasheet V1.0
Gotchas
Use the second exposed-pad size (5.72 mm) in the D1s/F133 footprint; the datasheet warns the package is built to it. The linux-sunxi D1s page lists an LFBGA 337 package, which is wrong: D1s is eLQFP128. Allwinner Online quotes the D1s CPU at 720 MHz while board vendors and the shared mainline OPP table use 1008 MHz. The C906 vector unit is XTheadVector (RVV 0.7.1), enabled in mainline only from 6.14 and not usable by RVV 1.0 toolchains. The Nezha drives VDD-CPU from a PWM-adjusted buck; mainline has no D1 PWM driver, so its device tree pins VDD-CPU at a fixed 1.1 V. Use an I2C-programmable or fixed regulator if you want DVFS on mainline.
Sources: Datasheet V1.0, Product brief, Other, git.kernel.org
Layout guides for the D1 / D1s's interfaces
Public layout guidance for each interface this chip has, from vendors who publish it, plus our calculators.
DDR3 / DDR3L
Fly-by command/address with termination at the end of the chain, point-to-point data lanes matched to their strobe, and a clean VREF. ST recommends 55 ohm single-ended and 100 ohm differential for DDR3 and DDR3L on STM32MP1 boards, and shows that a 4-layer board is possible with strict layer allocation.
- STM32MP1 Series DDR memory routing guidelinesSTMicroelectronics, AN5122, 3, 2019
- DDR3 Design Requirements for KeyStone DevicesTexas Instruments, SPRABI1, D, 2022
- SL2610 General PCB Design and DDR3L/DDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001629-01, A, 2025
- DDR length matching calculatorGroundplane calculator
eMMC
A single-ended bus: CLK, CMD, DAT0 to DAT7 and, for HS400, the data strobe. TI and Synaptics both route it at 50 ohm single-ended, match the group, and keep stubs short; Synaptics places a 22 or 33 ohm series resistor on CLK and STRB. At HS400 TI also checks the eMMC I/O supply impedance, not just the traces.
- AM62Px eMMC HS400 Board Design and Simulation GuidelinesTexas Instruments, SPRADP5, A, 2026
- Astra Machina Foundation Series eMMC ConfigurationSynaptics, PN 506-001594-01, D
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
SD card / SDIO
Single-ended CLK, CMD and four data lines over a solid ground plane, at constant trace width and matched length. NXP asks for clock-to-neighbor spacing greater than twice the trace height above the plane and 1.5 times for data and CMD, with 45 degree bends. UHS modes switch the I/O to 1.8 V, so a level translator often sits next to the socket.
- NVT4557/NVT4558/NVT4858 voltage-level translator layout guidelineNXP, AN13158, 1.1, 2022
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
- SD Physical Layer Simplified SpecificationSD Association, 9.10, 2023
PCIe
AC-coupled differential lanes routed with no stubs, minimal vias and back-drilled or blind vias where speed demands, with lane-to-lane skew handled by the receiver. Targets differ by guide: TI Jacinto 7 uses 85 ohm differential for lanes and 100 ohm for the reference clock, while TI's earlier SoC guide tabulates 100 ohm and, for some devices, 95 ohm. Match the target to your connector and stackup.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
USB 2.0
One D+/D- pair at 90 ohm differential, routed in parallel for its whole length with minimal deviations at the connector and package. NXP keeps clocks and periodic signals at least 50 mils away and other signals at least 20 mils away from the pair.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
HDMI
Four TMDS pairs (three data, one clock) at 100 ohm differential, as both TI guides state, with tight intra-pair matching and as few vias as possible between the SoC and the connector. HDMI also needs 5 V supply switching, DDC and CEC level handling, hot-plug detect and ESD at the connector.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- TPD12S016 PCB Layout Guidelines for HDMI ESDTexas Instruments, SLLA324, 2012
MIPI DSI
MIPI D-PHY clock and data lanes are routed as 100 ohm differential pairs over a solid reference; TI Jacinto 7 allows no stubs, 2 vias per trace and 40 ps lane-to-lane skew. Connectors and flex cables to the panel are usually the largest discontinuity, so keep the board segment short and clean.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex 5 FPGAs and SoCsAltera, 821801, 2026
MIPI CSI-2
Same D-PHY rules as DSI: 100 ohm differential lanes in both TI guides, with lane-to-lane skew bounded (40 ps in TI Jacinto 7). Size the lane count and lane rate from the sensor's output format before routing.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex 5 FPGAs and SoCsAltera, 821801, 2026
- MIPI CSI-2 bandwidth calculatorGroundplane calculator
LVDS
Tightly coupled differential pairs terminated at the receiver in 100 ohm, with TI's EMI guide asking for 100 ohm differential traces within 5 percent. Keep pairs matched and away from other aggressors, and avoid stubs and reference plane gaps along the route to the panel connector.
- LVDS Owner's Manual: Including High-Speed CML and Signal ConditioningTexas Instruments, SNLA187, 4th edition, 2008
- High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes DesignsTexas Instruments, SNLA302, 2018
- LVDS SerDes Gen I PCB and Interconnect Design-In GuidelinesTexas Instruments, SNLA008, A, 2018
Ethernet (RGMII / RMII)
TI routes MAC-to-PHY (MII family) traces at 50 ohm single-ended, under 6 inches, matched within 20 mils for gigabit, and the PHY-side MDI pairs at 100 ohm differential. RGMII also needs a 1.5 to 2.0 ns clock-to-data delay, added on the board or inside the MAC or PHY (RGMII-ID); decide which before layout so it is not applied twice.
- Ethernet PHY PCB Design Layout ChecklistTexas Instruments, SNLA387, 2021
- PCB Design Guideline for RGMII InterfaceRenesas, R01AN6272EJ0141, 1.41, 2026
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
Board-level design guides
Impedance and timing, power, thermal and ESD guidance that applies to any board around this chip.
Impedance and timing
Every high-speed interface on the board comes down to the same two numbers: the trace impedance your stackup actually gives, and the delay each trace adds. Set the stackup with your fab first, then route to its impedance table and match lengths in time, not millimeters, where the layers differ.
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- PCB impedance calculatorGroundplane calculator
- PCB propagation delay calculatorGroundplane calculator
Power delivery
For each switching regulator, place and route the input capacitor first, keep the switching current loop small, and keep the switch node short. Give the SoC rails solid planes and decoupling at the balls, and size current-carrying copper and vias for the real load.
- Five steps to a great PCB layout for a step-down converterTexas Instruments, SLYT614, 2015
- AN-1149 Layout Guidelines for Switching Power SuppliesTexas Instruments, SNVA021, C, 2013
- AN-1229 SIMPLE SWITCHER PCB Layout GuidelinesTexas Instruments, SNVA054, C, 2013
- Buck converter calculatorGroundplane calculator
- LDO power dissipation calculatorGroundplane calculator
- PCB trace width calculatorGroundplane calculator
- Via current calculatorGroundplane calculator
Thermal
Theta-JA is measured on a JEDEC test board that carries most of the heat, so it does not transfer directly to a product board; use it to compare packages and use the psi metrics for estimates. Thermal vias under the package, copper area and copper thickness move the most heat into the board.
- Semiconductor and IC Package Thermal MetricsTexas Instruments, SPRA953, D, 2024
- AN-2020 Thermal Design By Insight, Not HindsightTexas Instruments, SNVA419, C, 2013
- Heatsink thermal resistance calculatorGroundplane calculator
- LDO power dissipation calculatorGroundplane calculator
ESD protection
Place the TVS as close to the connector as design rules allow, route from the connector to the TVS with no stub, and keep the protected IC further from the TVS than the TVS is from the connector. Choose parts by clamping performance and by capacitance low enough for the interface speed.
- ESD Protection Layout GuideTexas Instruments, SLVA680, A, 2022
- Reading and Understanding an ESD Protection Data SheetTexas Instruments, SLLA305, A
- TPD12S016 PCB Layout Guidelines for HDMI ESDTexas Instruments, SLLA324, 2012
- PCB conductor spacing calculator (IPC-2221)Groundplane calculator
Allwinner's hardware design guide
Allwinner's hardware design guide, EVB reference schematics and DDR templates come from Allwinner or an authorized agent, usually under NDA, or through your SoM vendor. We do not link copies circulating elsewhere. The vendor schematics and open designs on the Boards tab are real, shipped layouts on the D1 / D1s and the best public reference.
BSP, mainline and toolkits
| Area | Status | Links |
|---|---|---|
| Vendor BSP kernel | Tina Linux (OpenWrt-based build system) with Linux 5.4 and U-Boot 2018, distributed by Allwinner Online through its SDK repo (account required); the same SDK supports D1-H and D1s. Allwinner also ships Melis RTOS for F133. The HiFi4 DSP, HDMI, video engine and audio codec are supported here, not in mainline.Checked 2026-10-13 | |
| Mainline Linux | Driver support arrived first: clocks and the cedrus video decoder compatible in 5.17, MMC and USB PHY in 5.18, DMA, display engine mixer and TCON in 5.19, T-Head cache and page-attribute errata and pinctrl in 6.0. ARCH_SUNXI for RISC-V, the D1/D1s SoC device trees and boards (Nezha, Lichee RV, Lichee RV Dock, Lichee RV 86 Panel, MangoPi MQ-Pro, MangoPi MQ, Dongshan Nezha STU) landed in 6.3 with EMAC, USB, MIPI DSI and I2S; crypto in 6.4; GPADC in 6.6; ClockworkPi v3.14 and DevTerm R-01 in 6.11; XTheadVector in 6.14; thermal sensor and LED controller nodes in 7.0. Not upstream as of 7.3-rc7: HDMI, a video engine node (so no hardware decode), the analog audio codec, the HiFi4 DSP, and the D1 PWM controller.Checked 2026-10-13 | |
| U-Boot and firmware | Mainline U-Boot has no RISC-V D1 board (only the shared sun20i DRAM driver used by T113/R528). Community boot chain: smaeul/sun20i_d1_spl for DRAM init, OpenSBI generic platform (D1 HSM support since v1.1), and the smaeul/u-boot d1-wip branch, which Buildroot's nezha_defconfig pins with OpenSBI 1.4 and Linux 6.6.22.Checked 2026-10-13 | |
| Distributions | Ubuntu publishes 24.04.5 LTS preinstalled server images for Allwinner Nezha and Sipeed LicheeRV Dock; 26.04 requires RVA23 and does not cover them. Buildroot has nezha, sipeed_lichee_rv and sipeed_lichee_rv_dock defconfigs. OpenWrt has a d1 target (kernel 6.18) with Nezha, Lichee RV Dock, MangoPi MQ-Pro and Dongshan Nezha STU images. Armbian lists Nezha as end of support and MangoPi MQ-Pro as community supported.Checked 2026-10-13 | |
| Tools | xfel (xboot) drives the BROM FEL mode over USB for D1 and F133, including DRAM init; Allwinner PhoenixSuit and PhoenixCard flash Tina images and are on the Allwinner Online download page.Checked 2026-10-13 | |
| Community | linux-sunxi wiki chip and board pages, the Allwinner Online forum (bbs.aw-ol.com), 100ask forums for the DongshanPI boards, Sipeed wiki for Lichee RV.Checked 2026-10-13 |
D1 / D1s system on modules
Any of these can sit on a carrier board we design.
| Module | Vendor | Connector | RAM | Design files | Price | Buy |
|---|---|---|---|---|---|---|
| Lichee RV (Nezha CM) | Sipeed | M.2 B-key style 67-pin edge, two sets (Sipeed wording) | 512 MB DDR3, 16-bit | Schematic PDF (Rev 1.0, KiCad), designator and dimension PDFs, 3D STEP, KiCad footprint library for the dock connector | ||
| Dongshan Nezha STU (core board) | 100ask (DongshanPI) | 512 MB DDR3 | Core board schematic PDF (V1.0) | |||
| YuzukiNezha D1s | YuzukiHD | 64 MB DDR2 (in D1s) | EasyEDA project archives (schematic and PCB); no license stated | |||
| ClockworkPi Core R-01 | ClockworkPi | 200-pin SODIMM for the ClockworkPi v3.14 mainboard | 1 GB DDR3 | Core module schematic PDF; v3.14 mainboard schematic PDF and Gerbers | USD 29 (ClockworkPi store, out of stock) |
Every public D1 / D1s board
| Board | Vendor | Type | RAM | Notable I/O | Design files | Price | Buy |
|---|---|---|---|---|---|---|---|
| Nezha (D1-H) | Allwinner Online | SBC, 85 x 56 mm, 6-layer PCB | 1 or 2 GB DDR3 (512 MB on early internal units) | GbE (RTL8211F), HDMI, MIPI DSI with touch, USB 2.0 host and OTG, XR829 Wi-Fi/BT, 256 MB SPI NAND, 40-pin header via PCF8574 | Schematic, placement and designator PDFs (2021-05-20) on the Allwinner Online download page (login required) | ||
| Lichee RV Dock | Sipeed | Carrier, 65 x 40 mm | HDMI, USB-A host, 2.4 GHz Wi-Fi/BT (optional), Speaker amp, analog mic, 30-pin mic array FPC | Schematic PDFs (dock and LCD extension), designator PDF, DXF and PDF dimensions, 3D | |||
| Lichee RV 86 Panel | Sipeed | Dev kit, 86 x 86 mm wall panel | 512 MB DDR3 on the core module per the panel page (the Sipeed comparison table says 1 GB) | 4 inch 480x480 or 720x720 IPS touch, XR829 Wi-Fi/BT, 100 Mbit Ethernet (RTL8201F), 2 digital mics, 5 V or 12 V input | Schematic PDF, dimensions (PDF, DXF), 3D STEP, printable shell STL | ||
| D1 Dock Pro | Sipeed | Carrier | Schematic PDF, designator PDFs, size PDF, 3D STEP, datasheet V1.0 | ||||
| MangoPi MQ-Pro | MangoPi | SBC, Raspberry Pi Zero size, 65 x 30 mm | 512 MB or 1 GB DDR3 | Mini HDMI, 2x USB-C (OTG, host), RTL8723DS Wi-Fi/BT, Pi Zero 40-pin header, RGMII/RMII FPC for an Ethernet board | Schematic PDF (v1.2) on mangopi.org; no layout found | ||
| Dongshan Nezha STU DIY base board | 100ask (DongshanPI) | Carrier | All unused pins to three 2x20 headers, No active circuitry | Schematic PDF, Altium project and PCB, Gerbers, BOM | |||
| DongshanPI-D1s | 100ask (DongshanPI) | SBC | 64 MB DDR2 (in D1s) | RGB and MIPI DSI displays, Wi-Fi/BT | Board schematic PDF (V2) and D1s stamp-hole core board schematic | ||
| Nezha D1s EVB | YuzukiHD with Allwinner Online | Dev kit | 64 MB DDR2 (in D1s) | RGB, MIPI DSI, touch, CVBS in and out, XR829 Wi-Fi/BT, FM radio, SD, SPI NOR, NAND boot | Full sources: EasyEDA Pro project, schematic PDF, Gerbers, BOM, pick and place, STEP (CERN-OHL-S-2.0) | ||
| DevTerm Kit R-01 | ClockworkPi | Dev kit, Portable terminal kit, 6.86 inch screen | 1 GB DDR3 | v3.14 mainboard (AXP228 battery PMIC), Thermal printer, Keyboard and trackball | Schematic PDFs for core, mainboard, extension, keyboard and battery boards; mainboard Gerbers | USD 245 (ClockworkPi store, out of stock) | |
| uConsole Kit R-01 | ClockworkPi | Dev kit, Handheld console kit | 1 GB DDR3 | USD 145 (ClockworkPi store, out of stock) |
Prices and links as checked on the dates in our data; the latest check on this page was 2026-10-13.
Boards with published design files
| Project | Author | Files | Tool | License |
|---|---|---|---|---|
| Nezha D1s EVB | YuzukiHD (with Allwinner Online) | EasyEDA Pro project, Schematic PDF, Gerbers, BOM (XLS), Pick and place, STEP and DXF | EasyEDA | CERN-OHL-S-2.0 |
| Xassette-Asterisk (D1s/F133, 2-layer) | SdtElectronics | KiCad schematic and PCB, F133 symbol library, BOM (CSV), 40-pin breakout board (KiCad) | KiCad | CERN-OHL-W-2.0 |
| YuzukiRV Router (D1s) | YuzukiHD | EasyEDA Pro project, Schematic PDF, Gerbers, STEP and DXF | EasyEDA | CERN-OHL-S-2.0 |
| YuzukiNezha D1s SoM | YuzukiHD | EasyEDA project archives (schematic and PCB) | EasyEDA | None stated in the repository |
| TinyEmbedded-Dual (F133/D1s or T113-S3) | yuansco | Altium schematic and PCB, Gerbers, BOM (CSV), Schematic PDF | Altium | None stated in the repository |
Buying the chip
Allwinner publishes no distributor list for these parts. Allwinner's product site now lists only F133 (and F135) from this family, while D1-H and D1s are gone from it and out of stock at LCSC; for a new design, F133-B is the part with visible stock. Datasheet tray quantities: 119 per tray for D1-H, 90 per tray for D1s and F133.
- LCSC: D1-H
- C5365284, LFBGA-337, out of stock; reference prices USD 7.20 at 1, 6.27 at 10, 5.70 at 30, 5.23 at 119 (tray of 119).
- LCSC: D1s
- C5365285, LQFP-128-EP, out of stock; reference prices USD 6.61 at 1, 5.75 at 10, 5.24 at 30, 4.80 at 90 (tray of 90).
- LCSC: F133-B
- C22438485, ELQFP-128, 101 in stock; USD 12.05 at 1, 10.36 at 10, 9.32 at 30, 8.46 at 90 (tray of 90). Datasheet V2.1 attached.
- Allwinner Online
- Its D1-H resource page lists a Taobao store for "development boards and chips"; the listing itself was not checked.
Datasheet, TRM and design documents
Linked where they are publicly hosted; we do not rehost Allwinner documents. These are third-party documents: we are not responsible for their accuracy, availability or confidentiality status. Disclosure.
- DatasheetAllwinner D1-H Datasheet (listed on the linux-sunxi D1 page)V1.0 · 2022-01-18 · community mirror (linux-sunxi), not hosted by Allwinner · checked 2026-10-13
- TRMAllwinner D1-H User Manual (listed on the linux-sunxi D1 page)V1.0 · 2022-01-18 · community mirror (linux-sunxi), not hosted by Allwinner · checked 2026-10-13
- DatasheetAllwinner D1 Datasheet (draft)V0.1 · 2021-03-02 · hosted by Sipeed · checked 2026-10-13
- TRMAllwinner D1 User Manual (draft)V0.1 · hosted by Sipeed · checked 2026-10-13
- DatasheetAllwinner D1s Datasheet (download page, login required)V1.0 · 2022-02-10 · hosted by Allwinner Online · checked 2026-10-13
- TRMAllwinner D1s User Manual and D1s Brief (download page, login required)V1.0 · hosted by Allwinner Online · checked 2026-10-13
- DatasheetAllwinner F133 Datasheet (F133-A, F133-B)V2.1 · 2023-11-17 · hosted by LCSC · checked 2026-10-13
- Product briefD1-H chip introduction and specificationshosted by Allwinner Online (docs.aw-ol.com) · checked 2026-10-13
- Product briefD1s chip introduction and specificationshosted by Allwinner Online (docs.aw-ol.com) · checked 2026-10-13
- OtherF133 product pagehosted by Allwinner · checked 2026-10-13
- OtherNezha D1-H board page (specs, 6-layer PCB, discrete power)hosted by Allwinner Online (docs.aw-ol.com) · checked 2026-10-13
- Board schematicSipeed Lichee RV schematic (D1 + 3x TMI3411 + DDR3)Rev 1.0 · 2021-11-02 · hosted by Sipeed · checked 2026-10-13
- Board schematicClockworkPi DevTerm R-01 core module schematic (SY8088/SY8089 + DDR3)hosted by ClockworkPi (GitHub) · checked 2026-10-13
- Board schematicMangoPi MQ-Pro schematic (MP2122 + DDR3)v1.2 · hosted by MangoPi (mangopi.org) · checked 2026-10-13
- OtherLinux sun20i-d1s.dtsi and sunxi-d1s-t113.dtsi (v7.3-rc7)hosted by kernel.org · checked 2026-10-13
- Otherlinux-sunxi D1 and D1s chip pages (list D1 V0.1, D1-H V1.0, D1s V1.0 datasheets and manuals, DE2.0 spec)community mirror (linux-sunxi.org), not hosted by Allwinner · checked 2026-10-13
Questions about the D1 / D1s
Not the D1 / D1s itself. We have designed and brought up boards on the Allwinner T507 and A527/T527, and on the Rockchip RV1106, RV1126, RV1126B, RK3566, RK3568, RK3576 and RK3588. The work carries over: power tree, DDR and high-speed layout, bring-up and the BSP, read against this chip's own datasheet.
D1-H Datasheet V1.0 and User Manual V1.0 (2022-01-18) are listed on the linux-sunxi D1 page; Sipeed hosts the earlier D1 Datasheet V0.1 draft (2021-03-02). Allwinner Online publishes the D1s Datasheet, User Manual and Brief V1.0 on its download page (free account required). LCSC hosts F133 Datasheet V2.1 (2023-11-17), which covers F133-A and F133-B.
D1 and D1-H are the same chip: external 16-bit DDR2/DDR3 up to 2 GB, HDMI 1.4, a HiFi4 DSP and 4K30 H.265 decode in a 13 x 13 mm BGA. D1s and F133 are the cost-down version in a 14 x 14 mm eLQFP128 with 64 MB DDR2 inside the package, no HDMI, no DSP and 1080p60 decode. F133-A drops CVBS input; F133-B keeps it.
Neither. The only graphics hardware is a 2D G2D engine, so desktops use software rendering (ClockworkPi lists the R-01 as "No GPU"). The C906 has a vector unit, but it implements T-Head's pre-ratification 0.7.1 vector draft (XTheadVector), which mainline Linux only enables from 6.14 and RVV 1.0 compilers do not target.
Enough for a headless or simple-display Linux box: CPU, clocks, pinctrl, MMC, USB, Ethernet, MIPI DSI and LCD display, I2S, crypto, GPADC and thermal are upstream (5.17 to 7.0), with board device trees from 6.3. Missing as of 7.3-rc7: HDMI, the hardware video decoder node, the analog audio codec, the HiFi4 DSP and the PWM controller. Mainline U-Boot has no D1 board, so boot uses smaeul's SPL and U-Boot fork with OpenSBI.
None in practice: Allwinner's own Nezha and every other public board we checked use discrete bucks for 0.9 V CPU, 0.9 V system and 1.5 V DDR3 (SY8088/SY8089, TMI3411 or MP2122), plus the SoC's two internal LDOs for 1.8 V analog and I/O. D1s/F133 boards can drop the DRAM rail regulator and feed the in-package DDR2 from the internal LDOB, at the cost of a lower ambient rating (70 C instead of 75 C).
Full design files: YuzukiHD Nezha D1s EVB and YuzukiRV Router (EasyEDA, CERN-OHL-S-2.0), SdtElectronics Xassette-Asterisk (KiCad, CERN-OHL-W-2.0) and yuansco TinyEmbedded-Dual (Altium, no license). 100ask also publishes Altium sources for its Nezha STU DIY base board, but in a repository that rehosts Allwinner design-kit files, so it is not linked. Sipeed, ClockworkPi, MangoPi and 100ask publish schematic PDFs for their D1-H boards but not layouts.
Related chips and reading
- T113HMI panels, CAN gateways, car displays, small Linux controllers
- RV1106 / RV1103Small AI cameras, tiny Linux nodes, IP KVMs
- V853 / V851AI IP cameras, door locks, access control
- RK3308Smart speakers, mic arrays, audio bridges, gateways
- RK3128 / RK3126TV boxes, tablets, low-cost HMIs
- A64Open-hardware SBCs, Linux phones and laptops, kiosks, education
- H618 / H616Pi Zero class SBCs, CM4-style 3D-printer SoMs, TV boxes, retro handhelds (H700)
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Links and facts on this page checked 2026-10-13. Spotted something out of date? Tell us through the contact form.
Compiled from publicly available sources: datasheets, technical reference manuals, vendor product pages, schematics and source code published by their owners and third parties. We link to documents where others host them and do not host, endorse or vouch for them. Everything on these pages, including our own specs, summaries, block diagrams, comparisons, calculators and design notes, is for reference only and may contain errors or be out of date. It is provided as is, and Groundplane is not responsible for errors in it, for third-party documents, or for any design, board or decision based on it. Always check the manufacturer's current datasheet, reference manual and design guidance before you design a board. Rockchip, Allwinner, Raspberry Pi and other product names are trademarks of their owners; we are not affiliated with any of them. See our disclosure.