RK3288
Quad Cortex-A17 32-bit SoC from 2014, still in mass production in its W versions at about USD 14 in single units, with 4K60 HDMI 2.0, H.265 decode and LVDS/eDP/dual MIPI DSI, but no PCIe, USB 3.0, SATA or NPU and a 4 GB address space.
- CPU
- 4x A17 up to 1.8 GHz (1.6 GHz on some parts)
- GPU
- Mali-T764 (4 cores)
- NPU
- None
- Video
- 4K60 H.265 / 4K24 H.264 decode, 1080p30 H.264 encode
- PCIe
- None
What the RK3288 is for
Right for
- Display-heavy products on a small budget: HDMI 2.0 at 4K60, eDP, dual-channel LVDS and two MIPI DSI from two display controllers (3840x2160 and 2560x1600)
- Digital signage and set-top style playback: H.265 Main10 decode to 4096x2304@60 plus TS input and CSA 2.0 descrambling on chip
- Maintaining or cost-reducing an existing RK3288 product: W-version parts are still listed MP and the bare chip is stocked at LCSC in single units
- Fully open boot chain on mainline: U-Boot initializes RK3288 DRAM from source (no rkbin DDR blob or BL31 needed), and Panfrost drives the Mali-T764
- Prototyping on well-documented boards: ASUS publishes schematic PDFs for every Tinker Board revision, Radxa for the Rock 2 SoM and baseboard
Wrong for
- Anything needing PCIe, USB 3.0, SATA or a second Ethernet MAC: the chip has none of them (one RGMII GMAC, USB 2.0 only)
- Edge AI: no NPU; RK3566/RK3568 add 0.8 to 1 TOPS at similar cost
- 64-bit software stacks: Cortex-A17 is ARMv7-A, so arm64 distributions, containers and toolchains do not run
- Designs needing more than 4 GB DRAM or LPDDR4: memory tops out at DDR3-1333 / LPDDR3-1066 with a 4 GB address space
- Video encode above 1080p30, or H.265 encode
Cost and constraints
- FCBGA636LD, 19 x 19 mm, 0.65 mm pitch, 0.35 mm balls; two 32-bit DRAM channels have to be routed, which pushes layer count up (the Radxa Rock 2 SoM is an 82 x 60 mm MXM card)
- BOM is the SoC (USD 14.48 at LCSC, qty 1), an RK808 or ACT8846 PMIC (often with extra SYR827/828 bucks for CPU and GPU rails) and two channels of DDR3 or LPDDR3
- Commercial temperature only: 0 to 80 C ambient for every part except RK3288K (-20 to 85 C, 1.6 GHz CPU and 500 MHz GPU outside 0 to 80 C)
- Thermal: datasheet simulation gives theta JA 16.1 C/W at 6.21 W on a 4-layer JEDEC board; plan a heatsink for sustained 1.8 GHz load
- Mainline video decode and display are usable, but the camera ISP and the H.264 encoder are not upstream; camera products stay on the vendor 4.4/4.19 kernels
Inside the RK3288
Drawn by Groundplane from the datasheet rev 2.7. Not Rockchip artwork.
- 2x 32-bit DDR3/3L, LPDDR2/3
- 4 GB address space
- eMMC 4.5
- SD 3.0
- Dual-channel NAND
- SPI boot
- 4x Cortex-A17 to 1.8 GHz
- 32 KB L1 I/D, 1 MB L2
- Neon, VFPv3
- Mali-T764, 4 cores
- 2D engine (RGA2)
- H.265 decode 4K60
- H.264 decode 4K24
- H.264/VP8 encode 1080p30
- JPEG codec, IEP
- ISP to 14 MP
- DVP camera interface
- VOP_BIG to 3840x2160
- VOP_LIT to 2560x1600
- Dual-channel DDR controller
- 100 KB SRAM, 20 KB boot ROM
- TrustZone, crypto engine
- Secure boot, eFuse
- 5 PLLs, 24 MHz osc
- PMU, 12 power domains
- 2x DMAC, 8 timers
- TSADC, SARADC
- GMAC RGMII/RMII
- USB 2.0 OTG
- 2x USB 2.0 host
- HSIC host
- 2x SDIO 3.0
- HDMI 2.0
- eDP 1.1 4-lane
- Dual-channel LVDS
- 2x MIPI DSI
- MIPI CSI, DVP
- 5x UART, 6x I2C, 3x SPI
- 4x PWM, SARADC
- I2S 8-ch, SPDIF
- TS in/out, smart card, PS/2
Read from the documents
Each value names the document it was read from.
| CPU | 4x Cortex-A17 (ARMv7-A), Neon and VFPv3, 32 KB L1 I/D each, 1 MB L2. Max 1.6 GHz (RK3288, RK3288 W, RK3288-D) or 1.8 GHz (RK3288-CG, RK3288-CG W, RK3288-C, RK3288K at 0 to 80 C) | Datasheet Rev 2.7, 1.2.1, Table 3-2 |
|---|---|---|
| GPU | Mali-T764, 4 shader cores, 256 KB L2, MMU; OpenGL ES 1.1/2.0/3.0, OpenCL 1.2, DirectX 11 (W version only). Max 500 MHz (RK3288, W, -D) or 600 MHz (-CG, -CG W, -C, K) | Datasheet Rev 2.7, 1.2.11, Table 3-2 |
| NPU | None | Datasheet Rev 2.7, 1.2 |
| Video decode | H.265 Main/Main10 up to 4096x2304@60; H.264 HP L5.1 up to 3840x2160@24; MPEG-4, MPEG-2, MPEG-1, VP8, AVS, MVC up to 1080p60; VC-1 1080p30; JPEG decode to 8176x8176 | Datasheet Rev 2.7, 1.2.6, 1.2.8, 1.2.9 |
| Video encode | H.264 (BP/MP/HP L4.0), VP8 and MVC up to 1920x1088@30, I and P slices only, 10 kbps to 20 Mbps; JPEG encode to 8192x8192 | Datasheet Rev 2.7, 1.2.7, 1.2.9 |
| Memory | Two channels, each 16 or 32-bit, 2 ranks per channel: DDR3-1333, DDR3L-1333, LPDDR2-1066, LPDDR3-1066; 4 GB total address space | Datasheet Rev 2.7, 1.2.4 |
| Storage | eMMC 4.5 (8-bit), SD 3.0 (4-bit), dual-channel 8-bit async/Toggle/ONFI NAND with 60-bit ECC; boot from NAND, SPI, eMMC or SD | Datasheet Rev 2.7, 1.2.3, 1.2.4 |
| Display | Two display controllers: VOP_BIG to 3840x2160, VOP_LIT to 2560x1600. HDMI 2.0 TX (4K60, HDCP 1.4; HDCP 2.2 and 4K YUV420 on W version), eDP 1.1 4 lanes (4Kx2K@30), dual-channel LVDS (not on RK3288-C), 2x MIPI DSI 4-lane, parallel RGB to 30-bit, BT.656 | Datasheet Rev 2.7, 1.2.12 to 1.2.16 |
| Camera | MIPI CSI-2 RX on two PHYs (MIPI1 shared with DSI TX, MIPI2 RX only), 4 lanes at up to 1 Gbps per lane; 8/10/12-bit DVP; ISP to 14 MP (4416x3312) | Datasheet Rev 2.7, 1.2.12, 1.2.15 |
| PCIe | None | Datasheet Rev 2.7, 1.2.18 |
| USB | 1x USB 2.0 OTG, 2x USB 2.0 host (EHCI host lacks USB 1.1 on non-W parts), 1x HSIC host | Datasheet Rev 2.7, 1.2.18, 1.2.20 |
| Ethernet | 1x GMAC 10/100/1000, RGMII or RMII | Datasheet Rev 2.7, 1.2.18 |
| Other I/O | 5x UART, 3x SPI, 6x I2C, 4x PWM, 160 GPIO, 3-ch 10-bit SARADC, 8-ch I2S/PCM, SPDIF, 2x SDIO 3.0, 2x TS in and 1x TS out with CSA 2.0, PS/2, smart card, HS-ADC, GPS baseband | Datasheet Rev 2.7, 1.2.17 to 1.2.19 |
| Security | TrustZone, crypto engine (AES-128/192/256, DES/TDES, SHA-1/256/512, HMAC, PKA to 3136-bit), TRNG, secure boot, eFuse 256 + 1024 bits | Datasheet Rev 2.7, 1.2.5, 1.2.19 |
| Process | 28 nm | Product brief |
| Package | FCBGA636LD, 19 x 19 mm, 0.65 mm pitch, 0.35 mm balls, 1.51 mm nominal height; the 18 x 18 mm FCCSP636LD version is EOL | Datasheet Rev 2.7, 2.1, Fig. 2-11, Fig. 2-12 |
| Temperature | 0 to 80 C ambient (RK3288K -20 to 85 C); Tj max 125 C; theta JA 16.1 C/W, theta JB 8.7 C/W, theta JC 0.4 C/W at 6.21 W (4-layer 2S2P board) | Datasheet Rev 2.7, Table 3-1, 3-2, 4-1 |
Variants
| RK3288 | Original part, FCBGA636LD. CPU 1.6 GHz, GPU 500 MHz, 0 to 80 C. Listed EOL in Rev 2.7 (MP in Rev 2.4). | Datasheet Rev 2.7 |
|---|---|---|
| RK3288 W version (RK3288W) | Die lot number ends in W. Same pinout. Adds HDCP 2.2 and 4K60 YUV 4:2:0 HDMI output, OHCI/USB 1.1 on the EHCI host, DirectX 11, RGA2 scaling fix, 4K IEP, updated ISP/DVP and I2C IO timing. Most changes need vendor software patches. CPU 1.6 GHz, GPU 500 MHz. MP. | Datasheet Rev 2.7 |
| RK3288-CG / RK3288-CG W | Higher-bin parts: CPU 1.8 GHz, GPU 600 MHz, 0 to 80 C. Plain -CG listed EOL in Rev 2.7, -CG W is MP. ASUS Tinker Board S R2.0 and R2.0 use RK3288-CG.W. | Datasheet Rev 2.7 |
| RK3288-C | For ChromeOS devices: CPU 1.8 GHz, GPU 600 MHz, no LVDS. MP. | Datasheet Rev 2.7 |
| RK3288K (W version) | Commercial wide-temperature part: -20 to 85 C ambient. CPU 1.8 GHz and GPU 600 MHz between 0 and 80 C, 1.6 GHz and 500 MHz below 0 C or above 80 C. MP (Rev 2.4 said it would be EOL in 2018; Rev 2.7 lists it MP). | Datasheet Rev 2.7 |
| RK3288-D | Added in Rev 2.5: 1.6 GHz CPU, 500 MHz GPU, "with Dolby function". MP. | Datasheet Rev 2.7 |
What to watch when you design with it
Size a heatsink for the RK3288 with its datasheet θJC and Tj max filled in, and download the STEP.
Power and PMIC
Two PMIC families appear on public RK3288 designs. Rockchip RK808 (ASUS Tinker Board, Tinker Board S and S R2.0 schematics all show RK808-B; Rockchip EVB-RK808 in mainline): four bucks (5 A, 5 A, 3 A, 2.5 A), eight LDOs, two switches, RTC, 2.7 to 5.5 V input, QFN68 7 x 7 mm; the datasheet block diagram maps BUCK1 to VDD_ARM, BUCK2 to VDD_LOGIC, BUCK3 to VCC_DDR and BUCK4 to VCC_IO. Active-Semi ACT8846 (Firefly-RK3288, Firefly Core-3288J, Boardcon CM3288, Radxa Rock 2 SoM, Rockchip EVB-ACT8846), where Radxa adds SYR827 and SYR828 bucks. SoC rails from the datasheet: CPU_VDD 0.9 to 1.4 V and LOGIC_VDD 0.9 to 1.35 V (typ 1.0 V), GPU_VDD 0.9 to 1.35 V, PMU_VDD_1V0, DDR IO 1.5 V (DDR3), 1.35 V (DDR3L) or 1.2 V (LPDDR2/3), and separate 1.0 V and 1.8 V analog rails for PLL, USB, HDMI, eDP, LVDS and MIPI. The 200 ohm USB REXT is required.
Sources: Datasheet Rev 2.7, PMIC Rev 1.6, Board schematic, Board schematic, Board schematic, download.t-firefly.com, armdesigner.com
DDR
Two independent channels, each 16 or 32-bit, up to two ranks each; DDR3/DDR3L at 1333 or LPDDR2/LPDDR3 at 1066, with a 4 GB total address space. Types cannot be mixed. The Tinker Board family uses 2 GB dual-channel LPDDR3; Firefly Core-3288J and the Boardcon modules use DDR3 (1 to 4 GB). We do not link Rockchip's DDR layout guidance for the RK3288, so copy a published layout reference: the Radxa Rock 2 SoM and Tinker Board schematics give the topology, but none of the RK3288 boards found publish layout files.
Sources: Datasheet Rev 2.7, Board schematic, Board schematic, download.t-firefly.com
High-speed interfaces
The fastest serial interfaces are HDMI 2.0 (up to 18 Gbps aggregate), eDP at 2.7 Gbps per lane, and MIPI at up to 1 Gbps per lane; everything else is USB 2.0, RGMII and SDIO. Three MIPI PHYs: MIPI0 is TX only, MIPI1 is TX or RX, MIPI2 is RX only, so a design with two DSI panels gives up one of the two CSI inputs. LVDS shares the display path and is absent on RK3288-C. HDCP 2.2 and 4K YUV 4:2:0 output need a W-version part.
Sources: Datasheet Rev 2.7
Boot and maskrom
The 20 KB boot ROM boots from 8-bit async or Toggle NAND, SPI, eMMC or SD, and accepts code download over the USB OTG port. Bring the OTG port to a connector. Firefly forces maskrom on its boards by shorting two marked test points with power off, then applying power; vendor tools (AndroidTool, upgrade_tool) flash from there. Mainline U-Boot builds RK3288 images without any Rockchip binary: DRAM init is open source (drivers/ram/rockchip/sdram_rk3288.c) and no BL31 is needed on this 32-bit part.
Sources: Datasheet Rev 2.7, wiki.t-firefly.com, github.com, github.com
Thermal
Datasheet simulation: theta JA 16.1 C/W, theta JB 8.7 C/W, theta JC 0.4 C/W with 6.21 W dissipation on a 4-layer 2S2P JEDEC board; Tj max 125 C. The ambient rating footnote says reference software limits the die to about 85 C, so sustained 1.8 GHz load throttles without a heatsink. ASUS ships a heatsink with the Tinker Board R2.0. Firefly rates its RK3288 modules and boards -20 to 60 C ambient.
Sources: Datasheet Rev 2.4, Datasheet Rev 2.7, tinker-board.asus.com, download.t-firefly.com
Gotchas
The video decoder (everything except H.265) and the H.264 encoder share an internal buffer and cannot run at the same time; only the separate HEVC block decodes alongside an encode. The W version needs vendor software patches to use its fixes (EHCI USB 1.1, HDCP 2.2, YUV420 4K). Rev 2.7 of the datasheet moved the plain RK3288 and RK3288-CG to EOL: specify a W-version part (RK3288 W, RK3288-CG W, RK3288K) for new builds.
Sources: Datasheet Rev 2.7
Layout guides for the RK3288's interfaces
Public layout guidance for each interface this chip has, from vendors who publish it, plus our calculators.
DDR3 / DDR3L
Fly-by command/address with termination at the end of the chain, point-to-point data lanes matched to their strobe, and a clean VREF. ST recommends 55 ohm single-ended and 100 ohm differential for DDR3 and DDR3L on STM32MP1 boards, and shows that a 4-layer board is possible with strict layer allocation.
- STM32MP1 Series DDR memory routing guidelinesSTMicroelectronics, AN5122, 3, 2019
- DDR3 Design Requirements for KeyStone DevicesTexas Instruments, SPRABI1, D, 2022
- SL2610 General PCB Design and DDR3L/DDR4 & LPDDR4(x) Interface Layout GuidelinesSynaptics, PN 506-001629-01, A, 2025
- DDR length matching calculatorGroundplane calculator
LPDDR3
Point-to-point and normally unterminated, with command/address matched to the clock and each byte matched to its strobe. ST gives the same targets for LPDDR3 as for DDR3: 55 ohm single-ended and 100 ohm differential. Few current public guides cover LPDDR3, so treat the SoC vendor's reference layout as the stronger source.
- STM32MP1 Series DDR memory routing guidelinesSTMicroelectronics, AN5122, 3, 2019
- DDR length matching calculatorGroundplane calculator
eMMC
A single-ended bus: CLK, CMD, DAT0 to DAT7 and, for HS400, the data strobe. TI and Synaptics both route it at 50 ohm single-ended, match the group, and keep stubs short; Synaptics places a 22 or 33 ohm series resistor on CLK and STRB. At HS400 TI also checks the eMMC I/O supply impedance, not just the traces.
- AM62Px eMMC HS400 Board Design and Simulation GuidelinesTexas Instruments, SPRADP5, A, 2026
- Astra Machina Foundation Series eMMC ConfigurationSynaptics, PN 506-001594-01, D
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
SD card / SDIO
Single-ended CLK, CMD and four data lines over a solid ground plane, at constant trace width and matched length. NXP asks for clock-to-neighbor spacing greater than twice the trace height above the plane and 1.5 times for data and CMD, with 45 degree bends. UHS modes switch the I/O to 1.8 V, so a level translator often sits next to the socket.
- NVT4557/NVT4558/NVT4858 voltage-level translator layout guidelineNXP, AN13158, 1.1, 2022
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
- SD Physical Layer Simplified SpecificationSD Association, 9.10, 2023
PCIe
AC-coupled differential lanes routed with no stubs, minimal vias and back-drilled or blind vias where speed demands, with lane-to-lane skew handled by the receiver. Targets differ by guide: TI Jacinto 7 uses 85 ohm differential for lanes and 100 ohm for the reference clock, while TI's earlier SoC guide tabulates 100 ohm and, for some devices, 95 ohm. Match the target to your connector and stackup.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
USB 2.0
One D+/D- pair at 90 ohm differential, routed in parallel for its whole length with minimal deviations at the connector and package. NXP keeps clocks and periodic signals at least 50 mils away and other signals at least 20 mils away from the pair.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
HDMI
Four TMDS pairs (three data, one clock) at 100 ohm differential, as both TI guides state, with tight intra-pair matching and as few vias as possible between the SoC and the connector. HDMI also needs 5 V supply switching, DDC and CEC level handling, hot-plug detect and ESD at the connector.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- TPD12S016 PCB Layout Guidelines for HDMI ESDTexas Instruments, SLLA324, 2012
DisplayPort / eDP
Main-link lanes are routed at 100 ohm differential in both TI guides, with no stubs and few vias; TI Jacinto 7 allows 2 vias per trace. When DisplayPort shares a USB-C connector through alt mode, the lanes run through the Type-C mux and the SuperSpeed rules apply to the shared path.
- High-Speed Layout Guidelines for Signal Conditioners and USB HubsTexas Instruments, SLLA414, A, 2026
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
MIPI DSI
MIPI D-PHY clock and data lanes are routed as 100 ohm differential pairs over a solid reference; TI Jacinto 7 allows no stubs, 2 vias per trace and 40 ps lane-to-lane skew. Connectors and flex cables to the panel are usually the largest discontinuity, so keep the board segment short and clean.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex 5 FPGAs and SoCsAltera, 821801, 2026
MIPI CSI-2
Same D-PHY rules as DSI: 100 ohm differential lanes in both TI guides, with lane-to-lane skew bounded (40 ps in TI Jacinto 7). Size the lane count and lane rate from the sensor's output format before routing.
- Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design GuidelinesTexas Instruments, SPRACP4, A, 2024
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex 5 FPGAs and SoCsAltera, 821801, 2026
- MIPI CSI-2 bandwidth calculatorGroundplane calculator
LVDS
Tightly coupled differential pairs terminated at the receiver in 100 ohm, with TI's EMI guide asking for 100 ohm differential traces within 5 percent. Keep pairs matched and away from other aggressors, and avoid stubs and reference plane gaps along the route to the panel connector.
- LVDS Owner's Manual: Including High-Speed CML and Signal ConditioningTexas Instruments, SNLA187, 4th edition, 2008
- High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes DesignsTexas Instruments, SNLA302, 2018
- LVDS SerDes Gen I PCB and Interconnect Design-In GuidelinesTexas Instruments, SNLA008, A, 2018
Ethernet (RGMII / RMII)
TI routes MAC-to-PHY (MII family) traces at 50 ohm single-ended, under 6 inches, matched within 20 mils for gigabit, and the PHY-side MDI pairs at 100 ohm differential. RGMII also needs a 1.5 to 2.0 ns clock-to-data delay, added on the board or inside the MAC or PHY (RGMII-ID); decide which before layout so it is not applied twice.
- Ethernet PHY PCB Design Layout ChecklistTexas Instruments, SNLA387, 2021
- PCB Design Guideline for RGMII InterfaceRenesas, R01AN6272EJ0141, 1.41, 2026
- i.MX28 Layout and Design GuidelinesNXP (Freescale), AN4215, 0, 2010
Board-level design guides
Impedance and timing, power, thermal and ESD guidance that applies to any board around this chip.
Impedance and timing
Every high-speed interface on the board comes down to the same two numbers: the trace impedance your stackup actually gives, and the delay each trace adds. Set the stackup with your fab first, then route to its impedance table and match lengths in time, not millimeters, where the layers differ.
- High-Speed Interface Layout GuidelinesTexas Instruments, SPRAAR7, J, 2023
- PCB impedance calculatorGroundplane calculator
- PCB propagation delay calculatorGroundplane calculator
Power delivery
For each switching regulator, place and route the input capacitor first, keep the switching current loop small, and keep the switch node short. Give the SoC rails solid planes and decoupling at the balls, and size current-carrying copper and vias for the real load.
- Five steps to a great PCB layout for a step-down converterTexas Instruments, SLYT614, 2015
- AN-1149 Layout Guidelines for Switching Power SuppliesTexas Instruments, SNVA021, C, 2013
- AN-1229 SIMPLE SWITCHER PCB Layout GuidelinesTexas Instruments, SNVA054, C, 2013
- Buck converter calculatorGroundplane calculator
- LDO power dissipation calculatorGroundplane calculator
- PCB trace width calculatorGroundplane calculator
- Via current calculatorGroundplane calculator
Thermal
Theta-JA is measured on a JEDEC test board that carries most of the heat, so it does not transfer directly to a product board; use it to compare packages and use the psi metrics for estimates. Thermal vias under the package, copper area and copper thickness move the most heat into the board.
- Semiconductor and IC Package Thermal MetricsTexas Instruments, SPRA953, D, 2024
- AN-2020 Thermal Design By Insight, Not HindsightTexas Instruments, SNVA419, C, 2013
- Heatsink thermal resistance calculatorGroundplane calculator
- LDO power dissipation calculatorGroundplane calculator
ESD protection
Place the TVS as close to the connector as design rules allow, route from the connector to the TVS with no stub, and keep the protected IC further from the TVS than the TVS is from the connector. Choose parts by clamping performance and by capacitance low enough for the interface speed.
- ESD Protection Layout GuideTexas Instruments, SLVA680, A, 2022
- Reading and Understanding an ESD Protection Data SheetTexas Instruments, SLLA305, A
- TPD12S016 PCB Layout Guidelines for HDMI ESDTexas Instruments, SLLA324, 2012
- PCB conductor spacing calculator (IPC-2221)Groundplane calculator
Rockchip's hardware design guide
Rockchip's hardware design guide, EVB reference schematics and DDR templates come from Rockchip or an authorized agent, usually under NDA, or through your SoM vendor. We do not link copies circulating elsewhere. The vendor schematics and open designs on the Boards tab are real, shipped layouts on the RK3288 and the best public reference.
BSP, mainline and toolkits
| Area | Status | Links |
|---|---|---|
| Vendor BSP kernel | Rockchip kernel trees carry RK3288 device trees on develop-4.4, develop-4.19 and develop-5.10 (EVB variants for RK808, RK818 and ACT8846, plus RK628 bridge examples on 4.19 and 5.10), and rk3288.dtsi is still present on develop-6.1, develop-6.6 and develop-6.12. Board vendor images (Firefly, ASUS Tinker OS, Boardcon) are 4.4 based.Checked 2026-10-13 | |
| Mainline Linux | rk3288.dtsi first appears in 3.17. Upstream nodes today cover CPU, clocks, GMAC, USB 2.0 and HSIC, eMMC/SD/SDIO, VOP_BIG and VOP_LIT with HDMI, eDP, LVDS and MIPI DSI outputs, RGA, crypto, efuse and the Mali GPU. Panfrost gained Mali-T760 (the T764) in 5.2. Hantro VPU: JPEG encode in 5.0 (staging), MPEG-2 decode in 5.3, H.264 and VP8 decode in 5.4; the driver now lives in drivers/media/platform/verisilicon. HEVC decode on the separate H.265 block (rkvdec RK3288 variant) landed in 6.19. No ISP or camera-interface node upstream as of 7.3-rc7. Board DTs moved to arch/arm/boot/dts/rockchip in 6.5. Tinker Board DT from 4.12, Tinker Board S from 5.0.Checked 2026-10-13 | |
| Chromebooks (Veyron) | Google Veyron devices are the reference users of mainline RK3288: DTs for Brain, Fievel, Jaq, Jerry, Mickey, Mighty, Minnie, Pinky, Speedy and Tiger are upstream, and mainline U-Boot has chromebook_jerry, chromebook_minnie, chromebook_speedy and chromebit_mickey configs. Their DTs are the best public example of an RK3288 eDP and power design in mainline form.Checked 2026-10-13 | |
| U-Boot | Mainline U-Boot supports EVB-RK3288-RK808, Firefly-RK3288, MiQi, Phytec PCM-947, PopMetal, Radxa Rock 2 Square, ROCK Pi N8, Tinker Board, Tinker Board S, Vyasa and four Chromebook targets, with open-source DRAM init. Rockchip vendor U-Boot (next-dev) has evb-rk3288, firefly, miqi, phycore, popmetal, tinker and vyasa configs; rkbin ships rk3288_ddr_400MHz_v1.12.bin and rk3288_miniloader_v2.63.bin for the vendor flow.Checked 2026-10-13 | |
| Video (MPP) | Rockchip MPP lists RK3288 among supported chips (develop branch, last pushed 2026-09-21).Checked 2026-10-13 | |
| 2D (RGA) | librga lists RK3288 and RK3288w as supported platforms (RGA2). Mainline has an RGA node and the rockchip-rga V4L2 driver.Checked 2026-10-13 | |
| NPU toolkit | Not applicable: the RK3288 has no NPU.Checked 2026-10-13 | |
| Android | Firefly publishes Android 5.1 firmware for Firefly-RK3288. Boardcon publishes Android 7.1 and Android 9 user manuals for the EM3288. ASUS publishes Android source for the Tinker Board on GitHub.Checked 2026-10-13 | |
| Distributions | Armbian lists the Tinker Board as Standard support with Armbian 26.8.1 images (Ubuntu 26.04 Xfce, Debian 13 minimal) on the current 6.18.43 kernel, built 2026-08-09. ASUS offers Tinker OS (Debian). Firefly offers Ubuntu, Debian and Buildroot firmware for Firefly-RK3288.Checked 2026-10-13 | |
| Community | Firefly-RK3288 wiki (boot modes, drivers, Linux and Android builds) and Tinker Board developer wiki on GitHub.Checked 2026-10-13 |
RK3288 on GitHub
Repositories for this chip: vendor code, mainline work, toolkits, distributions and open hardware.
- Vendor BSPJeffyCN/meta-rockchipYocto BSP layer maintained by a Rockchip engineer, with RK3288 and RK3288W machine configs. Last commit 2026-10.
- Kernelrockchip-linux/kernelRockchip BSP kernel; RK3288 runs from release-4.4 through develop-6.12 in arch/arm. Last commit 2026-08.
- KernelTinkerBoard/debian_kernelASUS Tinker Board Debian kernel source for RK3288. Last commit 2023-01.
- Kerneltorvalds/linuxMainline Linux has about 38 RK3288 device trees in arch/arm/boot/dts/rockchip. Last commit 2026-10.
- Bootloaderrockchip-linux/rkbinDDR init and loaders; bin/rk32 holds the rk3288 binaries. Last commit 2026-08.
- Bootloaderu-boot/u-bootMainline U-Boot with open SPL DDR init for RK3288 and Firefly, MiQi, Tinker Board and EVB configs. Last commit 2026-10.
- BootloaderTrustedFirmware-A/trusted-firmware-aRead-only mirror of TF-A; plat/rockchip/rk3288 is a 32 bit SP_MIN port for secure world on RK3288. Last commit 2026-10.
- Bootloadercoreboot/corebootRead-only mirror of coreboot; src/soc/rockchip/rk3288 boots the Veyron family Chromebooks. Last commit 2026-10.
- BootloaderTinkerBoard/debian_u-bootASUS Tinker Board Debian U-Boot source for RK3288. Last commit 2021-11.
- Mediarockchip-linux/mppMedia Process Platform; RK3288 is listed in the README for hardware decode and encode. Last commit 2026-09.
- Mediaairockchip/librgaRGA 2D acceleration library with RK3288 and RK3288W in its supported chip list. Last commit 2026-06.
- Distributionarmbian/buildArmbian build framework; Tinker Board is the supported RK3288 board, with MiQi and an XT-Q8L TV box as legacy configs. Last commit 2026-10.
- DistributionMichaIng/DietPiMinimal Debian images with an ASUS Tinker Board build for RK3288. Last commit 2026-10.
- DistributionLibreELEC/LibreELEC.tvKodi appliance OS with an RK3288 device under projects/Rockchip. Last commit 2026-10.
- Toolsrockchip-linux/rkdeveloptoolRockchip open source USB flashing tool for maskrom and loader mode, the Linux and macOS alternative to RKDevTool. Last commit 2025-03.
- Toolsxboot/xrockLow level maskrom and loader mode tool that can also init DDR and run code over USB; chip support is listed in its README. Last commit 2026-08.
- Toolslinux-rockchip/rkflashtoolCommunity rkflashtool fork for reading and writing flash over USB in loader mode; its device table includes RK3288. Last commit 2025-09.
RK3288 system on modules
Any of these can sit on a carrier board we design.
| Module | Vendor | Connector | RAM | Design files | Price | Buy |
|---|---|---|---|---|---|---|
| Core-3288J | Firefly | MXM 3.0 edge, 314 pins, 0.5 mm pitch | 1, 2 or 4 GB DDR3 (store sells 2 GB) | specification PDF only | USD 129 (Firefly store, 2 GB + 16 GB) | |
| Rock 2 SoM | Radxa | MXM 3.0 edge (MXM310 per Radxa) | 1, 2 or 4 GB DDR3 (with 4, 16 or 32 GB eMMC) | schematic PDF and component placement PDF (archived wiki) | ||
| ROCK Pi N8 (VMARC RK3288 SoM) | Radxa / Vamrs | SMARC-compatible edge (VMARC), Dalang carrier shared with ROCK Pi N10 | none found (archived wiki, hardware pages missing) | |||
| phyCORE-RK3288 (PCM-059) | PHYTEC | phyCORE board-to-board connectors | up to 4 GB DDR3 | hardware manual and component placement drawings (no schematic) | ||
| MINI3288 | Boardcon | 2x 100-pin board-to-board | DDR3 (512 MB default per manual; 2 GB in the EM3288 kit) | hardware manual with carrier circuit excerpts, connector drawing | ||
| CM3288 | Boardcon | board-to-board | 2 GB LPDDR3 (up to 4 GB) | hardware manual, 3D model (RAR) |
Every public RK3288 board
| Board | Vendor | Type | RAM | Notable I/O | Design files | Price | Buy |
|---|---|---|---|---|---|---|---|
| Tinker Board | ASUS | SBC, Raspberry Pi size SBC | 2 GB dual-channel LPDDR3 | HDMI, MIPI DSI and CSI, Gigabit Ethernet, 4x USB 2.0, 40-pin GPIO, Wi-Fi and Bluetooth | schematic PDF (zip), 2D and 3D drawings | ||
| Tinker Board S | ASUS | SBC, Raspberry Pi size SBC with eMMC | 2 GB dual-channel LPDDR3 | HDMI, MIPI DSI and CSI, Gigabit Ethernet, 4x USB 2.0, 40-pin GPIO, Wi-Fi and Bluetooth | schematic PDF, 2D and 3D drawings | ||
| Tinker Board R2.0 | ASUS | SBC, Raspberry Pi size SBC, RK3288-CG.W | 2 GB dual-channel LPDDR3 | HDMI, MIPI DSI and CSI, Gigabit Ethernet, 4x USB 2.0, 40-pin GPIO, Wi-Fi and Bluetooth | schematic PDF (Tinker Board S R2.0 schematic on the R2.0 documentation page) | ||
| Tinker Board S R2.0 | ASUS | SBC, Raspberry Pi size SBC with eMMC, RK3288-CG.W | 2 GB dual-channel LPDDR3 | HDMI, MIPI DSI and CSI, Gigabit Ethernet, 4x USB 2.0, 40-pin GPIO, Wi-Fi and Bluetooth | schematic PDF | ||
| Firefly-RK3288 | Firefly | Dev kit, Development board | 2 GB dual-channel DDR3 | HDMI 2.0, eDP, dual LVDS, MIPI DSI, MIPI CSI, Gigabit Ethernet (RTL8211E), 16 GB eMMC | none found on the current download page (firmware and tools only) | ||
| AIO-3288J | Firefly | Carrier, 182.8 x 107 mm industrial mainboard (Core-3288J on carrier) | 1, 2 or 4 GB DDR3 (store sells 2 GB) | HDMI 2.0 out, HDMI in to 1080p60 (option), Dual LVDS, eDP, Gigabit Ethernet, Wi-Fi and Bluetooth | specification PDF only | USD 189 (Firefly store, 2 GB + 16 GB, no HDMI-IN) | |
| AIO-3288C | Firefly | SBC, 126 x 91.3 mm mainboard | 2 GB dual-channel DDR3 | HDMI 2.0, Dual LVDS, eDP, Mini PCIe socket and SIM (USB modems), Gigabit Ethernet, VGA (variant) | specification PDF only | USD 134 (Firefly store, 2 GB + 8 GB) | |
| EC-A3288C | Firefly | Dev kit, Fanless embedded PC, 184 x 94 x 28 mm | 2 GB DDR3 | HDMI 2.0, Gigabit Ethernet, RS485, RS232, 4G/3G option, 8 GB eMMC | none | USD 219 (Firefly store) | |
| Rock 2 Square | Radxa | Carrier, Baseboard for the Rock 2 SoM | HDMI 2.0, eDP, LVDS header, Gigabit Ethernet, 1 OTG + 3 host USB 2.0, SPDIF, 40-pin header | schematic PDF (alpha and beta), placement PDF, DXF outline | |||
| EM3288 | Boardcon | SBC, MINI3288 SoM on carrier | 2 GB DDR3 | HDMI 2.0, VGA, LVDS, TTL LCD, Gigabit Ethernet (RTL8211E), SATA via bridge, 3x USB host, OTG, SIM and 4G option | hardware manual, overview diagram | ||
| Idea3288 | Boardcon | SBC, SBC | overview diagram only | ||||
| XPI-3288 | Geniatech | SBC, Credit-card size SBC | up to 2 GB LPDDR3 | HDMI, MIPI DSI and CSI, Gigabit Ethernet, 4x USB 2.0, 40-pin header, Wi-Fi and Bluetooth | specification PDF only |
Prices and links as checked on the dates in our data; the latest check on this page was 2026-10-13. Amazon links marked * are affiliate links; see our disclosure.
Buying the chip
Rockchip lists the RK3288 as "MP Now" on its product page. Datasheet Rev 2.7 marks the plain RK3288 and RK3288-CG EOL and the W versions, RK3288-C, RK3288K and RK3288-D as MP, so order a W-version part for new builds. Volume supply goes through Rockchip agents; Rockchip does not publish a distributor list we could confirm. Firefly and Boardcon still sell RK3288 modules from stock.
- LCSC: RK3288 (C191247)
- BGA-636, 700 per tray, listed 1.8 GHz and 0 to 80 C (suffix not stated). USD 14.48 at qty 1, USD 13.56 at qty 100; 26 in stock on 2026-10-13. MOQ 1.
Datasheet, TRM and design documents
Linked where they are publicly hosted; we do not rehost Rockchip documents. These are third-party documents: we are not responsible for their accuracy, availability or confidentiality status. Disclosure.
- DatasheetRockchip RK3288 Datasheet (file "RK3288 datasheet V2.7.pdf" in the listing)Rev 2.7 · 2019-12-27 · community mirror (rockchip.fr (community mirror)), not hosted by Rockchip · checked 2026-10-13
- DatasheetRockchip RK3288 DatasheetRev 2.4 · 2018-05-29 · hosted by Macro Group (distributor) · checked 2026-10-13
- DatasheetRockchip RK3288 DatasheetRev 1.5 · 2015-06-02 · hosted by LCSC (distributor) · checked 2026-10-13
- DatasheetRockchip RK3288 DatasheetRev 1.0 · 2014-05-16 · hosted by Radxa · checked 2026-10-13
- TRMRockchip RK3288 Technical Reference Manual, split by chapter (25 chapters)hosted by Radxa · checked 2026-10-13
- TRMRockchip RK3288 Technical Reference Manual (folder "RK3288 TRM" in the listing), split by chapter (33 chapters, adds GIC, RGA2, ISP, TS)community mirror (rockchip.fr (community mirror)), not hosted by Rockchip · checked 2026-10-13
- PMICRockchip RK808 Datasheet (RK808-B part listing)Rev 1.6 · 2019-08-27 · hosted by LCSC (distributor) · checked 2026-10-13
- Product briefRK3288 product page (key features and specifications)hosted by Rockchip · checked 2026-10-13
- Board schematicASUS Tinker Board schematic (RK3288 + RK808-B + LPDDR3), zip with PDF2016-09-20 · hosted by ASUS · checked 2026-10-13
- Board schematicASUS Tinker Board S schematichosted by ASUS · checked 2026-10-13
- Board schematicASUS Tinker Board S R2.0 schematic (RK3288-CG.W + RK808-B)hosted by ASUS · checked 2026-10-13
- Board schematicRadxa Rock 2 SoM schematic (RK3288 + ACT8846 + DDR3)2014-09-27 · hosted by Radxa · checked 2026-10-13
- Board schematicRadxa Rock 2 Square baseboard schematic (beta)2015-03-03 · hosted by Radxa · checked 2026-10-13
- OtherPHYTEC phyCORE-RK3288 Hardware ManualL-826e_1 · hosted by PHYTEC · checked 2026-10-13
- OtherBoardcon CM3288 Hardware ManualV2 · hosted by Boardcon · checked 2026-10-13
- OtherBoardcon MINI3288 Hardware User ManualV4 · hosted by Boardcon · checked 2026-10-13
Questions about the RK3288
Not the RK3288 itself. We have designed and brought up boards on the Rockchip RV1106, RV1126, RV1126B, RK3566, RK3568, RK3576 and RK3588, and on the Allwinner T507 and A527/T527. The work carries over: power tree, DDR and high-speed layout, bring-up and the BSP, read against this chip's own datasheet.
The newest public revision is Rev 2.7 (2019-12-27), on the rockchip.fr community mirror. Macro Group, a Rockchip distributor, hosts Rev 2.4 (2018-05-29); LCSC hosts Rev 1.5 and Radxa the original Rev 1.0. The TRM is public only split by chapter: 25 chapters on Radxa's download server and 33 on rockchip.fr. Rockchip's own product page has a one-page feature summary.
Same die and FCBGA636 package. The W version (lot number ending in W) adds HDCP 2.2, 4K YUV420 HDMI output, USB 1.1 on the EHCI host and several bug fixes, some needing vendor software patches. RK3288-C is the ChromeOS part: 1.8 GHz CPU, 600 MHz GPU and no LVDS. The plain RK3288 runs at 1.6 GHz and 500 MHz and is EOL in datasheet Rev 2.7; RK3288-CG W is the 1.8 GHz part in production.
Yes in its W versions. Rockchip's product page says "MP Now", and datasheet Rev 2.7 lists RK3288 W, RK3288-C, RK3288K, RK3288-D and RK3288-CG W as MP, with the plain RK3288 and RK3288-CG EOL. LCSC had 26 bare chips in stock at USD 14.48 each on 2026-10-13.
Yes, and better than most Rockchip parts of its age, largely because of the Veyron Chromebooks. CPU, Ethernet, USB, storage, HDMI, eDP, LVDS, MIPI DSI and the Mali-T764 (Panfrost, since 5.2) are upstream; Hantro decodes H.264, VP8 and MPEG-2 and encodes JPEG, and HEVC decode landed in 6.19. The ISP is not upstream. Mainline U-Boot boots it with no Rockchip binaries. Armbian builds Tinker Board images on kernel 6.18.
The RK3288 is 32-bit only (Cortex-A17), has no PCIe, USB 3.0 or NPU, and tops out at 4 GB DDR3/LPDDR3. RK3399 adds two A72 cores, PCIe 2.1 x4 and USB 3.0; RK3568 adds PCIe 3.0, SATA, two GMACs and a 1 TOPS NPU. Pick the RK3288 only for a display-centric 32-bit product where its cost, mainline maturity or an existing design matters more than I/O.
Firefly Core-3288J (MXM 3.0, 314 pins, USD 129 in stock on 2026-10-13), Boardcon MINI3288 (2x 100-pin) and CM3288 (-20 to 85 C, LPDDR3), PHYTEC phyCORE-RK3288 (45 x 42 mm), and the older Radxa Rock 2 SoM (MXM, schematic published) and Vamrs VMARC RK3288 (ROCK Pi N8).
Related chips and reading
- RK3399Mainline-first products, laptops, NAS, routers, HMI
- RK3568Routers, NAS, gateways, NVR, industrial HMI
- RK3566HMI, e-ink readers, handhelds, CM4-class SoMs, small routers
- RK3328Routers, TV boxes, Klipper hosts
- RK3128 / RK3126TV boxes, tablets, low-cost HMIs
We'll design your RK3288 board.
Tell us the interfaces, power budget and volume. An engineer replies with questions or a proposal.
Links and facts on this page checked 2026-10-13. Spotted something out of date? Tell us through the contact form.
Compiled from publicly available sources: datasheets, technical reference manuals, vendor product pages, schematics and source code published by their owners and third parties. We link to documents where others host them and do not host, endorse or vouch for them. Everything on these pages, including our own specs, summaries, block diagrams, comparisons, calculators and design notes, is for reference only and may contain errors or be out of date. It is provided as is, and Groundplane is not responsible for errors in it, for third-party documents, or for any design, board or decision based on it. Always check the manufacturer's current datasheet, reference manual and design guidance before you design a board. Rockchip, Allwinner, Raspberry Pi and other product names are trademarks of their owners; we are not affiliated with any of them. See our disclosure.