UART baud rate calculator
The divisor, actual baud rate and error for a UART clock, and whether the total clock mismatch fits the budget a receiver can tolerate.
- Actual baud rate
- 115,384.6 bit/s
- Divisor
- 13
- Link budget, total mismatch
- 3.29 % 16x sampling, 10-bit frame, 75% window.
- Total mismatch used
- 0.18 % Pass
| Baud | Divisor | Actual | Error | Within ±3.29% |
|---|---|---|---|---|
| 1.2 k | 1250 | 1,200 | 0.000% | OK |
| 2.4 k | 625 | 2,400 | 0.000% | OK |
| 4.8 k | 313 | 4,792 | -0.160% | OK |
| 9.6 k | 156 | 9,615 | 0.160% | OK |
| 19.2 k | 78 | 19,231 | 0.160% | OK |
| 38.4 k | 39 | 38,462 | 0.160% | OK |
| 57.6 k | 26 | 57,692 | 0.160% | OK |
| 115.2 k | 13 | 115,385 | 0.160% | OK |
| 230.4 k | 7 | 214,286 | -6.994% | Over budget |
| 460.8 k | 3 | 500,000 | 8.507% | Over budget |
| 921.6 k | 2 | 750,000 | -18.620% | Over budget |
| 1 M | 2 | 750,000 | -25.000% | Over budget |
| 1.5 M | 1 | 1,500,000 | 0.000% | OK |
| 2 M | - | - | - | Clock too slow |
| 3 M | - | - | - | Clock too slow |
How this is calculated
divisor = round( fclk / ( OS · baud ) · k ) / k k = 1 integer, 16 or 8 fractional baud actual = fclk / ( OS · divisor ) error = baud actual / baud − 1 budget = ( OS · w / 2 − 1 ) / ( OS · ( N − 0.5 ) )
- Budget
- After Maxim AN2141: the receiver syncs on the start bit edge to within one sample clock and must sample the last stop bit, N − 0.5 bits later, inside the usable window w of the bit. w is 75% on a clean link and 50% on a poor one. At 16x and 8N1 that is 5/152 = 3.3% and 3/152 = 2.0%, the AN2141 figures.
- Total mismatch
- The budget is the total difference between transmitter and receiver. Divisor error at this end plus clock tolerance at both ends plus the far end divisor error must fit inside it.
- Divisor
- Integer divisors follow the 16550 scheme: divisor = clock / (16 × baud), held in 16 bits (TL16C550D). Fractional divisors round to 1/16 or 1/8 of a step; check the fraction width in your reference manual.
- Not covered
- Jitter and edge distortion on the line, which eat into the window before clock error does. The 8x budget applies the AN2141 method at 8 samples per bit.
- Maxim Integrated Application Note 2141, Determining Clock Accuracy Requirements for UART Communications30 June 2003
- Texas Instruments TL16C550D datasheet, Tables 9 and 10 (baud rates from 1.8432 and 3.072 MHz)SLLS597E, revised December 2008
Questions
Maxim AN2141 puts the total mismatch a 16x UART tolerates on an 8N1 frame at 3.3% for a short, clean link and 2% for a long, capacitive RS-232 run. That total is shared between both ends, so if both use the same divisor scheme each side gets roughly half: about 1.6% on a clean link and 1% on a poor one.
16 MHz / (16 × 115200) = 8.68, which rounds to 9 and gives 111111 baud, 3.5% slow. That is outside both budgets. A fractional divisor in 1/16 steps reaches 8.6875 and an error of 0.08%; 8x oversampling with an integer divisor gives 17 and 2.1%.
They divide exactly to standard rates. 1.8432 MHz / 16 = 115200, so every rate that divides 115200 has zero divisor error. The TL16C550D table for 1.8432 MHz shows non-zero error only at 110, 134.5, 2000 and 56000 baud (2.86% at 56000).
Yes. With parity the frame is 11 bits and the last sample sits 10.5 bits after the start edge, so the clean-link budget at 16x falls from 5/152 = 3.3% to 5/168 = 3.0%.
For clock tolerance, yes. The one-sample sync uncertainty is a larger share of the bit, so on a clean 8N1 link the budget falls from 3.3% to 2/76 = 2.6%. The benefit is twice the maximum baud rate from the same clock.